Replace msleep by cond_resched. On machines with HZ=100 (e.g. ARM)
msleep slows down the operation by factor 10
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This driver does not have as many options but it's easier to maintain.
And, it turns out AMD never shipped boards with different flash densities.
Signed-off-by: Pete Popov <ppopov@pacbell.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Alexander Nyberg <alexn@dsv.su.se>
Signed-off-by: Joern Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Check timeout while we wait for the command to finish. No worry about a
false result. This prevents deadlocking when detecting an unknown number
of chips and is useful for removable media too.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Do not use the ready function here, as it might hang for ever.
The result will show, whether the chip is there or not
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Fix sparse errors due to lack of address-space markers
Updated header comments
Small re-format of initialiser
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
update the BAST driver config (which already supports the vr1000) to
be selected only if the vr1000 has been configured
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Scan 1st and 2nd pages of SP devices for BB marker by default.
Fix more then one page scanning in create_bbt.c.
Signed-off-by: Artem B. Bityuckiy <dedekind@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Move manufacturer ID search to display correct ID in case of buswidth
mismatch.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The change to the generic probe to look for the
smallest width of chip first is causing some problems
on boards with a single 16bit device.
The problem seems to be the jedec_match() is truncating
the device-id read from the table to match against the
one read from the hardware, causing a match against the
partial id of some chips with 16bit IDs (such as the
SST39LF160)
This fixes things for my own board, but something may
need to be done if the same problem is exhibited for
chips with an 8bit ID
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
When scanning NAND for bad blocks, don't read the whole page, read
only needed OOB bytes instead. Also check the return code of the
nand_read_raw() function. Correctly free the this->bbt array in
case of failure. Tested with Large page NAND.
Fix debugging message.
Signed-off-by: Artem B. Bityuckiy <dedekind@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Small bugfix. Sometimes it may be handy not to have bbt.
So, this->bbt might be NULL.
Signed-off-by: Artem B. Bityuckiy <dedekind@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This is implemented using a ioctl to switch the MTD char device into
one of the different OTP "modes", at which point read/write/seek can
operate on the selected OTP area. Also some extra ioctls to query
for size and lock protection segments or groups. Some example user
space utilities are provided.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This enables support for reading, writing and locking so called
"Protection Registers" present on some flash chips.
A subset of them are pre-programmed at the factory with a
unique set of values. The rest is user-programmable.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* Removed table entry for AM29BDS643D, since device ID clashes with AM29DL640G
and both chips support CFI.
Signed-off-by: Jonas Holmberg <jonas.holmberg@axis.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Try larger numbers of chips before smaller
numbers of chips across the bus width.
This means we'll avoid misdetecting a 2 x16 array as 1 x32 if the
high 16-bits happen to read as zeros in the QRY area.
Signed-off-by: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Added routine to perform extra error status checks on erase and write
failures to determine if errors are correctable.
Added option to prevent JFFS2 from using virtual erase blocks.
Performed minor cleanup on whitespace and comments.
Signed-off-by: David A. Marlin <dmarlin@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Add optional hardware specific callback routine to perform extra error
status checks on erase and write failures for devices with hardware ECC.
Signed-off-by: David A. Marlin <dmarlin@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Driver for generic RAM blocks which are exported by an platform_device
from the device driver system.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Ensure the whole device is added if there are no partitions found on the
device, so that at least the flash can be read/written.
Replace some of the constants with their SZ_xxx counterparts
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Add routine to perform device recovery (deplete) procedure.
Clean up some compiler warnings.
Signed-off-by: David A. Marlin <dmarlin@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Added workaround for Renesas AG-AND chips "disturb" issue
for Bad Block Table.
Added support for the device recovery command sequence
for Renesas AG-AND chips.
Signed-off-by: David A. Marlin <dmarlin@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Added extended commands for AG-AND device and added
option for BBT_AUTO_REFRESH.
Signed-off-by: David A. Marlin <dmarlin@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
For the case that mtd partitions are enabled it would cause a 0-pointer
dereferencing in mtdpart.c:mtd_erase_callback()
Signed-off-by: Herbert Valerio Riedel <hvr@inso.tuwien.ac.at>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Add error checks to read/write functions and add an eraseblock size.
Makes slram a suitable device for JFFS2.
Signed-off-by: Josh Boyer <jdub@us.ibm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The latest speedbumped Apple G5 models have a "bug" in the Open Firmware
device tree that lacks the proper interrupt routing information for the
northbridge i2c controller. Apple's driver silently falls back into a
sub-optimal "polled" mode (heh, maybe they didn't even notice the bug
because of that :), our driver didn't properly check and crashes :(
This patch fixes our driver to not crash, and adds code to the
prom_init() OF trampoline code that detects the "bug" and adds the
missing information back for this chipset revision. This fixes booting
and thermal control on these models.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
with high-speed mode enabled, we switch it to high-speed mode so that
baud_base becomes 921600. However, we also need to multiply the baud
divisor by 8 at the same time, in case it's already in use as a console.
Signed-off-by: David Woodhouse
Acked-by: Tom Rini
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Defines for the different command classes as defined in the MMC and SD
specifications.
Removes the check for high command classes and instead checks that the
command classes needed are present.
Previous solution killed forward compatibility at no apparent gain.
Signed-of-by: Pierre Ossman
If you tried to open a packet device first in read-only mode and then a
second time in read-write mode, the second open succeeded even though the
device was not correctly set up for writing. If you then tried to write
data to the device, the writes would fail with I/O errors.
This patch prevents that problem by making the second open fail with
-EBUSY.
Signed-off-by: Peter Osterlund <petero2@telia.com>
Cc: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
The new period/dt setting routines don't get the coupling of these
parameters correct. This means that Domain Validation never gets DT
set, and thus the drive gets restricted to U80.
Fix this by restoring the couplings in the set routines.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Tampering with the settings has to be done under the host lock ...
slave_alloc isn't called under any lock, so this has to be done
explicitly.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
The allocation of all of our components should be done in slave alloc.
Currently it's rather fancifully refcounted in the queuecommand
callback. This patch moves allocation and destroy to their correct
places in slave_alloc/slave_destory. Now we can guarantee that
everywhere a device is requested, it's actually been allocated, so don't
check for this anymore.
Additionally, the per device busy timer was the only source of potential
use after free. It's been deleted because Linux does the correct thing
with busy returns, so there's no need to implement a separate timer in
the driver.
Finally, implement code that forces all the device parameters to zero
(i.e. async and narrow) in the slave alloc, inform the spi class of the
bios recorded maximums and wait until slave configure before trying
anything more adventurous.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
This should finish the spurious queue removal from aic7xxx (there are
other queues that are probably unnecessary, but at least the major and
obviously unnecessary ones are done with).
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
This was rendered obsolete by the busyq removal; remove some of the last
remnants of its presence.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
pci_alloc_consistent is under 4G by default. Also simplify the
definition of bus_dmamap_t.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
