Commit graph

26255 commits

Author SHA1 Message Date
Kevin D. Kissell
8531a35e5e [MIPS] SMTC: Fix SMTC dyntick support.
Rework of SMTC support to make it work with the new clock event system,
allowing "tickless" operation, and to make it compatible with the use of
the "wait_irqoff" idle loop.  The new clocking scheme means that the
previously optional IPI instant replay mechanism is now required, and has
been made more robust.

Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03 17:58:58 +01:00
Kevin D. Kissell
d2bb01b042 [MIPS] SMTC: Close tiny holes in the SMTC IPI replay system.
Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03 17:58:58 +01:00
Kevin D. Kissell
9cc123631b [MIPS] SMTC: Fix holes in SMTC and FPU affinity support.
Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03 17:58:58 +01:00
Ralf Baechle
498a863fdf [MIPS] SMTC: Build fix: Fix filename in Makefile
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03 17:58:57 +01:00
Ralf Baechle
b7e4226e4f [MIPS] Build fix: Fix irq flags type
Though from a hardware perspective it would be sensible to use only a
32-bit unsigned int type Linux defines interrupt flags to be stored in
an unsigned long and nothing else.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03 17:58:56 +01:00
Jonathan Cameron
c46c948260 [ARM] 5278/1: i2c-pxa fast mode support
Add fast_mode option to i2c_pxa_platform_data and use it to set the
ICR_FM bit appropriately when i2c_pxa_reset is called. Parameter
called fast_mode rather than frequency as this driver is also used
for the i2c_pxa_pwr bus which has different normal and fast frequencies.

Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-03 15:57:06 +01:00
Catalin Marinas
000b502592 [ARM] 5229/3: Replace some ARMv7 opcodes with the instruction name
These instructions were placed in the code directly as opcodes because
early compilers didn't support them. Toolchains supporting ARMv7
understand these instructions and the patch puts the mnemonics back.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-03 11:32:09 +01:00
Hartley Sweeten
92e88aa7fb [ARM] 5276/1: ep93xx: allow selecting UART for early kernel messages
Currently on the EP93xx platform early kernel messages go to UART1.
Since this UART is the only one that has modem control signals it
might be used for another purpose and it is undesirable for those
messages to appear. This patch allows one of the other UARTs to be
selected in the kernel configuration. It is assumed that the
bootloader has configured and initialized the UART since this was the
previous assumption.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-03 11:03:39 +01:00
Dmitry Baryshkov
ec36b16d0d [ARM] 4733/1: export sharpsl_param
EXPORT sharpsl_param which is necessary to support modular build of some depending drivers.

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-03 10:18:35 +01:00
Russ Anderson
175e438f7a x86: trivial printk fix in efi.c
[patch] x86: Trivial printk fix in efi.c

The following line is lacking a space between "memdesc" and "doesn't".

  "Kernel-defined memdescdoesn't match the one from EFI!"

Fixed the printk by adding a space.

Signed-off-by: Russ Anderson <rja@sgi.com>
Cc: Russ Anderson <rja@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-10-03 10:18:30 +02:00
Yinghai Lu
8bb39311bf x86, debug: mtrr_cleanup print out var mtrr before change it
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-10-03 09:50:04 +02:00
Yinghai Lu
834836ee6a x86: mtrr_cleanup try gran_size to less than 1M, v3
J.A. Magallón reported:

 >> Also, on a 64 bit box with 4Gb, it gives this:
 >>
 >> cicely:~# cat /proc/mtrr
 >> reg00: base=0x00000000 (   0MB), size=4096MB: write-back, count=1
 >> reg01: base=0x100000000 (4096MB), size=1024MB: write-back, count=1
 >> reg02: base=0x140000000 (5120MB), size= 512MB: write-back, count=1
 >> reg03: base=0x160000000 (5632MB), size= 256MB: write-back, count=1
 >> reg04: base=0x80000000 (2048MB), size=2048MB: uncachable, count=1

boundary handling has a problem ... fix it.

Reported-by: J.A. Magallón <jamagallon@ono.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-10-03 09:41:55 +02:00
J.A. Magallón
136c82c6f7 x86: mtrr_cleanup try gran_size to less than 1M, cleanup
Patch below cleans up formatting, with space for big bases and sizes (64 Gb).

Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-10-03 09:41:42 +02:00
Kristoffer Ericson
49ea26d0a0 [ARM] 5277/1: Add basic support for MobilePro 900/c
This patch adds basic support for the Mobilepro
900/c mini-laptop. At present it won't do much
more than build and boot.

Signed-off-by: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-02 22:56:05 +01:00
Marek Vašut
4e9687d9c8 [ARM] 5248/1: wm97xx generic battery driver
This patch adds generic battery driver for wm97xx chips.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-02 22:48:34 +01:00
Nicolas Pitre
3319f5e51a [ARM] 5274/1: simplify request_standard_resources()
There is no point converting memory bank addresses from physical to
virtual just to convert them back to physical addresses.  Furthermore
this isn't "right" for highmem even if in this case the end result is
the correct one.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-02 22:46:21 +01:00
FUJITA Tomonori
40becd8d5a AMD IOMMU: use iommu_device_max_index
AMD IOMMU can use iommu_device_max_index() instead of the homegrown
function.

Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-10-02 11:33:41 +02:00
Kumar Gala
1fce2d01df powerpc: Fix boot hang regression on MPC8544DS
Commit 00c5372d37 caused the MPC8544DS
board to hang at boot.  The MPC8544DS is unique in that it doesn't use
the PCI slots on the ULI (unlike the MPC8572DS or MPC8610HPCD).  So
the dummy read at the end of the address space causes us to hang.

We can detect the situation by comparing the bridge's BARs versus
the root complex.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-02 00:58:49 -05:00
Jürgen Schindele
2532967147 [ARM] 5251/1: remove old LED support for Trizeps4 SOM
Remove the old led support in arch/arm/mach-pxa/leds...
for TRIZEPS4 SOM. It is / will be replaced by generic
led driver drivers/leds/...

Signed-off-by: Jürgen Schindele <linux@schindele.name>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 22:34:34 +01:00
Jürgen Schindele
642aa6637e [ARM] 5204/1: Trizeps4 SOM update
- use MFP-API for GPIO
- support TRIZEPS4WL module
- cleanups

Signed-off-by: Jrgen Schindele <linux@schindele.name>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 22:33:11 +01:00
Kristoffer Ericson
bda0308609 [ARM] 5270/1: Fix Formatting in mach-sa1100/ machine files
This patch fixes formatting issues in mach-sa1100/
machine files. More specificly badge4.c,generic.c and
pleb.c.

Signed-off-by: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 22:29:43 +01:00
Kristoffer Ericson
89c816b948 [ARM] 5256/1: Update jornada default config
This patch updates the jornada default
config (which was made for 2.6.12). Plenty
of development has happend since then, most
importantly the SSP driver and kbd/touchscr.

This config has been tested to compile
and bootup properly.

Signed-off-by: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 22:29:33 +01:00
Russell King
4ba3f7c559 [ARM] mm: allow LH7A40x to use sparsemem
Enable Sparsemem support for LH7A40x SoCs, while still allowing the
existing discontig support for the time being.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 21:42:08 +01:00
Russell King
07a2f737ba [ARM] mm: deprecate discontigmem on ARM
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 21:41:32 +01:00
Russell King
ee93916efe [ARM] mm: switch SA1100 to use sparsemem
Tested on Assabet, and Assabet with Neponset's SDRAM at 3328M phys.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 21:03:21 +01:00
Linus Torvalds
edfd222fc5 Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, vmi: fix broken LDT access
  x86: fix typo in enable_mtrr_cleanup early parameter
2008-10-01 12:26:49 -07:00
David Howells
d6478fad43 MN10300: Fix IRQ handling
Fix the IRQ handling on the MN10300 arch.

This patch makes a number of significant changes:

 (1) It separates the irq_chip definition for edge-triggered interrupts from
     the one for level-triggered interrupts.

     This is necessary because the MN10300 PIC latches the IRQ channel's
     interrupt request bit (GxICR_REQUEST), even after the device has ceased to
     assert its interrupt line and the interrupt channel has been disabled in
     the PIC.  So for level-triggered interrupts we need to clear this bit when
     we re-enable - which is achieved by setting GxICR_DETECT but not
     GxICR_REQUEST when writing to the register.

     Not doing this results in spurious interrupts occurring because calling
     mask_ack() at the start of handle_level_irq() is insufficient - it fails
     to clear the REQUEST latch because the device that caused the interrupt is
     still asserting its interrupt line at this point.

 (2) IRQ disablement [irq_chip::disable_irq()] shouldn't clear the interrupt
     request flag for edge-triggered interrupts lest it lose an interrupt.

 (3) IRQ unmasking [irq_chip::unmask_irq()] also shouldn't clear the interrupt
     request flag for edge-triggered interrupts lest it lose an interrupt.

 (4) The end() operation is now left to the default (no-operation) as
     __do_IRQ() is compiled out.  This may affect misrouted_irq(), but
     according to Thomas Gleixner it's the correct thing to do.

 (5) handle_level_irq() is used for edge-triggered interrupts rather than
     handle_edge_irq() as the MN10300 PIC latches interrupt events even on
     masked IRQ channels, thus rendering IRQ_PENDING unnecessary.  It is
     sufficient to call mask_ack() at the start and unmask() at the end.

 (6) For level-triggered interrupts, ack() is now NULL as it's not used, and
     there is no effective ACK function on the PIC.  mask_ack() is now the
     same as mask() as the latch continues to latch, even when the channel is
     masked.

Further, the patch discards the disable() op implementation as its now the same
as the mask() op implementation, which is used instead.

It also discards the enable() op implementations as they're now the same as
the unmask() op implementations, which are used instead.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-10-01 09:40:43 -07:00
Russell King
07f841b7c5 [ARM] mm: enable sparsemem on clps7500 and RiscPC
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 17:24:04 +01:00
Russell King
b7a69ac303 [ARM] mm: finish ARM sparsemem support
... including some comments about the ordering required to bring
sparsemem up.  You have to repeatedly guess, test, reguess, try
again and again to work out what the right ordering is.  Many
hours later...

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 17:24:04 +01:00
Russell King
d2a38ef9c1 [ARM] mm: provide helpers for accessing membanks
Provide helpers for getting physical addresses or pfns from the
meminfo array, and use them.  Move for_each_nodebank() to
asm/setup.h alongside the meminfo structure definition.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 17:22:02 +01:00
Russell King
8ec53663d2 [ARM] Improve non-executable support
Add support for detecting non-executable stack binaries, and adjust
permissions to prevent execution from data and stack areas.  Also,
ensure that READ_IMPLIES_EXEC is enabled for older CPUs where that
is true, and for any executable-stack binary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:10 +01:00
Russell King
5ec9407dd1 [ARM] Don't include asm/elf.h in asm code
asm code really wants asm/hwcap.h, so include that instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:10 +01:00
Russell King
9b727abdff [ARM] Remove MT_NONSHARED_DEVICE alias
Use MT_DEVICE_NONSHARED instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:07 +01:00
Russell King
db5b716947 [ARM] Remove MT_DEVICE_IXP2000 and associated definitions
As of the previous commit, MT_DEVICE_IXP2000 encodes to the same
PTE bit encoding as MT_DEVICE, so it's now redundant.  Convert
MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:06 +01:00
Russell King
40df2d1d85 [ARM] Update Xscale and Xscale3 PTE mappings
Use 'shared device' mappings for devices, and use the standard
bit combinations for Xscale3.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:04 +01:00
Russell King
40d192b63d [ARM] remove 'prot_pte_ext' from memory type table
This member is now redundant; the memory type is encoded in the Linux
PTE bits.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:02 +01:00
Russell King
3f69c0c1af [ARM] Convert ARMv7 to use TEX remapping
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:01 +01:00
Russell King
639b0ae7f5 [ARM] Convert ARMv6 and ARMv7 to use new memory types
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:00 +01:00
Russell King
9e8b5199a7 [ARM] Convert Xscale and Xscale3 to use new memory types
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:58 +01:00
Russell King
bb30f36f9b [ARM] Introduce new PTE memory type bits
Provide L_PTE_MT_xxx definitions to describe the memory types that we
use in Linux/ARM.  These definitions are carefully picked such that:

1. their LSBs match what is required for pre-ARMv6 CPUs.
2. they all have a unique encoding, including after modification
   by build_mem_type_table() (the result being that some have more
   than one combination.)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:56 +01:00
Russell King
9cff96e5bf [ARM] Re-jig Linux PTE bits to allow room for 4 memory type bits
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:54 +01:00
Russell King
da0916539d [ARM] Convert set_pte_ext implementions to macros
There are actually only four separate implementations of set_pte_ext.
Use assembler macros to insert code for these into the proc-*.S files.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:52 +01:00
David S. Miller
b262e60309 Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:

	drivers/net/wireless/ath9k/core.c
	drivers/net/wireless/ath9k/main.c
	net/core/dev.c
2008-10-01 06:12:56 -07:00
Yinghai Lu
2ffb3501f6 x86: change MTRR_SANITIZER to def_bool y
This option has been added in v2.6.26 as a default-disabled
feature and went through several revisions since then.

The feature fixes a wide range of MTRR setup problems that BIOSes
leave us with: slow system, slow Xorg, slow system when adding lots
of RAM, etc., so we want to enable it by default for v2.6.28.

See:

  [Bug 10508] Upgrade to 4GB of RAM messes up MTRRs
  http://bugzilla.kernel.org/show_bug.cgi?id=10508

and the test results in:

   http://lkml.org/lkml/2008/9/29/273

1. hpa
reg00: base=0xc0000000 (3072MB), size=1024MB: uncachable, count=1
reg01: base=0x13c000000 (5056MB), size=  64MB: uncachable, count=1
reg02: base=0x00000000 (   0MB), size=4096MB: write-back, count=1
reg03: base=0x100000000 (4096MB), size=1024MB: write-back, count=1
reg04: base=0xbf700000 (3063MB), size=   1MB: uncachable, count=1
reg05: base=0xbf800000 (3064MB), size=   8MB: uncachable, count=1

will get
Found optimal setting for mtrr clean up
gran_size: 1M   chunk_size: 128M        num_reg: 6      lose RAM: 0M
range0: 0000000000000000 - 00000000c0000000
Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
hole: 00000000bf700000 - 00000000c0000000
Setting variable MTRR 2, base: 3063MB, range: 1MB, type UC
Setting variable MTRR 3, base: 3064MB, range: 8MB, type UC
range0: 0000000100000000 - 0000000140000000
Setting variable MTRR 4, base: 4096MB, range: 1024MB, type WB
hole: 000000013c000000 - 0000000140000000
Setting variable MTRR 5, base: 5056MB, range: 64MB, type UC

2. Dylan Taft
reg00: base=0x00000000 (   0MB), size=4096MB: write-back, count=1
reg01: base=0x100000000 (4096MB), size= 512MB: write-back, count=1
reg02: base=0x120000000 (4608MB), size= 256MB: write-back, count=1
reg03: base=0xd0000000 (3328MB), size= 256MB: uncachable, count=1
reg04: base=0xe0000000 (3584MB), size= 512MB: uncachable, count=1
reg05: base=0xc7e00000 (3198MB), size=   2MB: uncachable, count=1
reg06: base=0xc8000000 (3200MB), size= 128MB: uncachable, count=1

will get
Found optimal setting for mtrr clean up
gran_size: 1M   chunk_size: 4M  num_reg: 6      lose RAM: 0M
range0: 0000000000000000 - 00000000c8000000
Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
Setting variable MTRR 2, base: 3072MB, range: 128MB, type WB
hole: 00000000c7e00000 - 00000000c8000000
Setting variable MTRR 3, base: 3198MB, range: 2MB, type UC
rangeX: 0000000100000000 - 0000000130000000
Setting variable MTRR 4, base: 4096MB, range: 512MB, type WB
Setting variable MTRR 5, base: 4608MB, range: 256MB, type WB

3. Gabriel
reg00: base=0xd0000000 (3328MB), size= 256MB: uncachable, count=1
reg01: base=0xe0000000 (3584MB), size= 512MB: uncachable, count=1
reg02: base=0x00000000 (   0MB), size=4096MB: write-back, count=1
reg03: base=0x100000000 (4096MB), size= 512MB: write-back, count=1
reg04: base=0x120000000 (4608MB), size= 128MB: write-back, count=1
reg05: base=0x128000000 (4736MB), size=  64MB: write-back, count=1
reg06: base=0xcf600000 (3318MB), size=   2MB: uncachable, count=1

will get
Found optimal setting for mtrr clean up
gran_size: 1M   chunk_size: 16M         num_reg: 7      lose RAM: 0M
range0: 0000000000000000 - 00000000d0000000
Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
Setting variable MTRR 2, base: 3072MB, range: 256MB, type WB
hole: 00000000cf600000 - 00000000cf800000
Setting variable MTRR 3, base: 3318MB, range: 2MB, type UC
rangeX: 0000000100000000 - 000000012c000000
Setting variable MTRR 4, base: 4096MB, range: 512MB, type WB
Setting variable MTRR 5, base: 4608MB, range: 128MB, type WB
Setting variable MTRR 6, base: 4736MB, range: 64MB, type WB

4. Mika Fischer
reg00: base=0xc0000000 (3072MB), size=1024MB: uncachable, count=1
reg01: base=0x00000000 ( 0MB), size=4096MB: write-back, count=1
reg02: base=0x100000000 (4096MB), size=1024MB: write-back, count=1
reg03: base=0xbf700000 (3063MB), size= 1MB: uncachable, count=1
reg04: base=0xbf800000 (3064MB), size= 8MB: uncachable, count=1

will get
Found optimal setting for mtrr clean up
gran_size: 1M   chunk_size: 16M         num_reg: 5      lose RAM: 0M
range0: 0000000000000000 - 00000000c0000000
Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB
Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB
hole: 00000000bf700000 - 00000000c0000000
Setting variable MTRR 2, base: 3063MB, range: 1MB, type UC
Setting variable MTRR 3, base: 3064MB, range: 8MB, type UC
rangeX: 0000000100000000 - 0000000140000000
Setting variable MTRR 4, base: 4096MB, range: 1024MB, type WB

Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-10-01 08:35:44 +02:00
Russell King
6c5da7aced [ARM] mm: move vmalloc= parsing to arch/arm/mm/mmu.c
There's no point scattering this around the tree, the parsing
of the parameter might as well live beside the code which uses
it.  That also means we can make vmalloc_reserve a static
variable.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 21:34:16 +01:00
Russell King
eca73214c9 [ARM] mm: move validation of membanks to one place
The newly introduced sanity_check_meminfo() function should be
used to collect all validation of the meminfo array, which we
have in bootmem_init().  Move it there.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 21:34:15 +01:00
Zachary Amsden
dc63b52673 x86, vmi: fix broken LDT access
This one took a long time to rear up because LDT usage is not very
common, but the bug is quite serious.  It got introduced along with
another bug, already fixed, by 75b8bb3e56

After investigating a JRE failure, I found this bug was introduced a long time
ago, and had already managed to survive another bugfix which occurred on the
same line.  The result is a total failure of the JRE due to LDT selectors not
working properly.

Signed-off-by: Zachary Amsden <zach@vmware.com>
Cc: Glauber de Oliveira Costa <gcosta@redhat.com>
Cc: stable@kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-09-30 21:13:18 +02:00
Zachary Amsden
de59985e3a x86: Fix broken LDT access in VMI
After investigating a JRE failure, I found this bug was introduced a
long time ago, and had already managed to survive another bugfix which
occurred on the same line.  The result is a total failure of the JRE due
to LDT selectors not working properly.

This one took a long time to rear up because LDT usage is not very
common, but the bug is quite serious.  It got introduced along with
another bug, already fixed, by 75b8bb3e56

Signed-off-by: Zachary Amsden <zach@vmware.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Glauber de Oliveira Costa <gcosta@redhat.com>
Cc: <stable@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-09-30 11:16:34 -07:00
Nicolas Pitre
99c6bb390c [ARM] Feroceon: small cleanups to L2 cache code
- Make sure that coprocessor instructions for range ops are contiguous
  and not reordered.

- s/invalidate_and_disable_dcache/flush_and_disable_dcache/

- Don't re-enable I/D caches if they were not enabled initially.

- Change some masks to shifts for better generated code.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Lennert Buytenhek <buytenh@marvell.com>
2008-09-30 13:41:54 -04:00
Linus Torvalds
d3a47e82b6 Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
  [IA64] Put the space for cpu0 per-cpu area into .data section
2008-09-30 09:47:16 -07:00