In d7e81c2 (clocksource: Add clocksource_register_hz/khz interface) new
interfaces were added which simplify (and optimize) the selection of the
divisor shift/mult constants. Switch over to using this new interface.
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Ensure that no interrupt is pending before registering the clock
event device, and properly initialize the periodic tick in the
->set_mode callback.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The AXI protocol specifies that the write response can only
be sent back to an AXI master when the last write data has been
accepted. This optimization enables the PL310 to send the write
response of certain write transactions as soon as the store buffer
accepts the write address. This behavior is not compatible with
the AXI protocol and is disabled by default. You enable this
optimization by setting the Early BRESP Enable bit in the
Auxiliary Control Register (bit [30]).
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enabling L2 prefetching improves performance as shown on Panda
ES2.1 board with mem test, and it has measurable impact on
performances. I think we should consider it, even though it damages
"writes" a bit. (rebased to k.org)
Usually the prefetch is used at both levels together L1 + L2, however,
to enable the CP15 prefetch engines, these are under security, and on
GP devices, we cannot enable it(e.g. on PandaBoard). However, just
enabling PL310 prefetch seems to provide performance improvement,
as shown in the data below (from Ubuntu) and would be a great thing
to pull in.
What prefetch does is enable automatic next line prefetching. With this
enabled, whenever the PL310 receives a cachable read request, it
automatically prefetches the following cache line as well.
Measurement Data:
==
STOCK 10.10 WITHOUT PATCH
========================
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2aaad000 0x2b2ad000
copy libc 133 MB/s
copy Android v5 273 MB/s
copy Android NEON 235 MB/s
copy INT32 116 MB/s
copy ASM ARM 187 MB/s
copy ASM VLDM 64 204 MB/s
copy ASM VLDM 128 173 MB/s
copy ASM VLD1 216 MB/s
read ASM ARM 286 MB/s
read ASM VLDM 242 MB/s
read ASM VLD1 286 MB/s
write libc 1947 MB/s
write ASM ARM 1943 MB/s
write ASM VSTM 1942 MB/s
write ASM VST1 1935 MB/s
10.10 + PATCH
=============
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2ab17000 0x2b317000
copy libc 129 MB/s
copy Android v5 256 MB/s
copy Android NEON 356 MB/s
copy INT32 127 MB/s
copy ASM ARM 321 MB/s
copy ASM VLDM 64 337 MB/s
copy ASM VLDM 128 321 MB/s
copy ASM VLD1 350 MB/s
read ASM ARM 496 MB/s
read ASM VLDM 470 MB/s
read ASM VLD1 488 MB/s
write libc 1701 MB/s
write ASM ARM 1682 MB/s
write ASM VSTM 1693 MB/s
write ASM VST1 1681 MB/s
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch removes the hardcoded value of auxctrl value and
construct it using bitfields
Bit 25 is reserved and is always set to 1. Same value
of this bit is retained in this patch
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds the PL310 Auxiliary Control Register bitfields
so that SOC's can use these bit fields to construct the AUXCTRL
value to be passed/programmed instead of hardcoding it.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We should not be incrementing mm_users when we startup a secondary
CPU - doing so results in mm_users incrementing by one each time we
hotplug a CPU, which will eventually wrap, and will cause problems.
Other architectures such as x86 do not increment mm_users, but only
mm_count, so we follow that pattern.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since CPU_PJ4 is shared between PXA95x and MMP2, select CPU_PJ4 in MMP2
configuration.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Saarb platform is a handheld platform that supports Marvell PXA955 silicon.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
The core of PXA955 is PJ4. Add new PJ4 support. And add new macro
CONFIG_PXA95x.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Commit f2ce623126 (OMAP: WDT: Split OMAP1 and OMAP2PLUS device
registration) removed omap_init_wdt and related structures from
plat-omap/devices.c. However a subsequent commit or merge
seems to have reintroduced these by accident. The caller of
omap_init_wdt was also removed by that commit, and this did
not get restored. So we have the following build warning now:
CC arch/arm/plat-omap/devices.o
arch/arm/plat-omap/devices.c:252: warning: 'omap_init_wdt' defined but not used
Fix this by removing this dead code.
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
New assemblers need -march=armv7-a+sec on command line or
.arch_extension sec inline to enable use of the smc instruction.
This patch uses as-instr to check the latter to conditionally
enable the former in AFLAGS for files that use smc.
Checked on both old and new binutils to verify that it does
not break old versions.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch will kill following section mismatch warnings:
WARNING: vmlinux.o(.text+0x24a00): Section mismatch in reference from the function zoom_twl_gpio_setup() to the (unknown reference) .init.data:(unknown)
The function zoom_twl_gpio_setup() references
the (unknown reference) __initdata (unknown).
This is often because zoom_twl_gpio_setup lacks a __initdata
annotation or the annotation of (unknown) is wrong.
WARNING: vmlinux.o(.text+0x24bfc): Section mismatch in reference from the function cm_t35_twl_gpio_setup() to the (unknown reference) .init.data:(unknown)
The function cm_t35_twl_gpio_setup() references
the (unknown reference) __initdata (unknown).
This is often because cm_t35_twl_gpio_setup lacks a __initdata
annotation or the annotation of (unknown) is wrong.
WARNING: vmlinux.o(.data+0x1d3e0): Section mismatch in reference from the variable h4_config to the (unknown reference) .init.data:(unknown)
The variable h4_config references
the (unknown reference) __initdata (unknown)
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
WARNING: vmlinux.o(.data+0x1dc08): Section mismatch in reference from the variable sdp2430_config to the (unknown reference) .init.data:(unknown)
The variable sdp2430_config references
the (unknown reference) __initdata (unknown)
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
WARNING: vmlinux.o(.data+0x1e1d8): Section mismatch in reference from the variable apollon_config to the (unknown reference) .init.data:(unknown)
The variable apollon_config references
the (unknown reference) __initdata (unknown)
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Power to the wl12xx wlan device is controlled by a fixed regulator.
Boards that have the wl12xx should select REGULATOR_FIXED_VOLTAGE so
users will not be baffled.
Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add comments and IDs for the following erratas:
- i540: MPU cannot exit from Standby,
- i478: Unexpected Cold-Reset is generated when device is coming
back from OFF mode
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add minimal support for Nokia RM-680 board.
Tested with omap2plus_defconfig.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
[tony@atomide.com: updated to remove omap_gpio_init
Signed-off-by: Tony Lindgren <tony@atomide.com>
Introduce 97.6/195.2 MHz memory timing data. Based on patches by Eduardo
Valentin, Igor Dmitriev and Juha Keski-Saari.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Cc: Eduardo Valentin <eduardo.valentin@nokia.com>
Cc: Igor Dmitriev <ext-dmitriev.igor@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Actually check for errors: print an error log and return NULL.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use an array to make it easier to add new values.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rename the current timings to indicate they're for 166 MHz. Based on
patches by Eduardo Valentin and Juha Keski-Saari.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Cc: Eduardo Valentin <eduardo.valentin@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a header file for Nokia SDRAM functions. Based on patches by Juha
Keski-Saari.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rename the file and functions so that it can be reused by future Nokia
boards. Based on patches by Juha Keski-Saari.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As PControl G20 is a carrier board for the Stamp9G20 SoM, some code can
be shared. Therefore board-stamp9g20.c is refactored to allow reusing the
SoM initialization and board-pcontrol-g20.c is modified to use it.
Signed-off-by: Christian Glindkamp <christian.glindkamp@taskit.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The uhpck clock should be divided from the utmi clock, not its parent
(main). This change is mostly cosmetic as the uhpck rate value is not
used anywhere except for the debugfs clock output.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Fix interrupt priority level handling on SH-Mobile ARM.
SH-Mobile ARM platforms using multiple interrupt priority
levels need this patch to fix a potential dead lock that
may occur if multiple interrupts with different levels
are pending simultaneously.
The default INTC configuration is to use the same priority
level for all interrupts, so this issue does not trigger by
default. It is however common for board code to override the
interrupt priority for certain interrupt sources depending
on the application. Without this fix such boards may lock up.
In detail, this patch updates the INTC code in entry-macro.S
to make sure that the INTLVLA register gets set as expected.
To trigger this bug modify the board specific code to adjust
the interrupt priority level for the ethernet chip. After
changing the priority level simply use flood ping to drown
the board with interrupts.
This patch applies to INTCA-based processors such as sh7372,
sh7377 and sh7372. GIC-based processors are not affected.
Suitable for v2.6.37-rc and stable from v2.6.34 to v2.6.36.
Cc: stable@kernel.org
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Turn down the warning noise from the compiler,
basically a SH-Mobile specific version of the
patch located in the RMK patch tracker:
6484/1: "fix compile warning in mm/init.c",
Without this patch the following warning triggers:
CC arch/arm/kernel/sys_arm.o
arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int'
CC arch/arm/kernel/traps.o
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds new entries required by the new version of MAX8998
driver. Without them, the driver fails to init. See commit 50f19a4596
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
S3C2416 PM code uses low-level sleep routines from S3C2412 code,
but these routines are compiled only for S3C2412 SoC.
Split S3C2412_PM to two parts: S3C2412_PM, S3C2412_PM_SLEEP and
select last in S3C2416's Kconfig.
Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add USB OTG, peripheral and host devices. This patch also adds
usb_phy_clk which is required for resetting the PHY. VBUS power up
and shutdown routines depends on PMIC module. As PMIC driver is
unavailable, configure USB in peripheral only mode.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
OTG driver takes care of putting hardware into low power mode. Hence
make peripheral and host devices as children of OTG device and let
runtime PM takes care of notifying peripheral and host state to
OTG device. VBUS power up and shutdown routines are implemented by
modem processor. As RPC infrastructure is not available, configure
USB in peripheral only mode.
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
* usb-next: (132 commits)
USB: uas: Use GFP_NOIO instead of GFP_KERNEL in I/O submission path
USB: uas: Ensure we only bind to a UAS interface
USB: uas: Rename sense pipe and sense urb to status pipe and status urb
USB: uas: Use kzalloc instead of kmalloc
USB: uas: Fix up the Sense IU
usb: musb: core: kill unneeded #include's
DA8xx: assign name to MUSB IRQ resource
usb: gadget: g_ncm added
usb: gadget: f_ncm.c added
usb: gadget: u_ether: prepare for NCM
usb: pch_udc: Fix setup transfers with data out
usb: pch_udc: Fix compile error, warnings and checkpatch warnings
usb: add ab8500 usb transceiver driver
USB: gadget: Implement runtime PM for MSM bus glue driver
USB: gadget: Implement runtime PM for ci13xxx gadget
USB: gadget: Add USB controller driver for MSM SoC
USB: gadget: Introduce ci13xxx_udc_driver struct
USB: gadget: Initialize ci13xxx gadget device's coherent DMA mask
USB: gadget: Fix "scheduling while atomic" bugs in ci13xxx_udc
USB: gadget: Separate out PCI bus code from ci13xxx_udc
...
Extend the perf_pmu_register() interface to allow for named and
dynamic pmu types.
Because we need to support the existing static types we cannot use
dynamic types for everything, hence provide a type argument.
If we want to enumerate the PMUs they need a name, provide one.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <20101117222056.259707703@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Define all IRQs in irqs.h. If some IRQs are sharing one IRQ number, define
them together. If some IRQs are sharing same name with different IRQ number,
define different IRQ.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
After introducing pxa930/pxa935 and new silicons, original cpuid rules
of XScale generation 3 can't fit new silicons. Now redefine the rule
of PXA3xx.
Only PXA300/PXA310/PXA320/PXA930/PXA935 are family members of PXA3xx.
PXA930/PXA935 are family members of PXA93x. PXA93x can be considered
as PXA3xx + CP.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
