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3 commits

Author SHA1 Message Date
David Daney
b93b2abce4 MIPS: Octeon: Rewrite DMA mapping functions. 
All Octeon chips can support more than 4GB of RAM.  Also due to how Octeon
PCI is setup, even some configurations with less than 4GB of RAM will have
portions that are not accessible from 32-bit devices.

Enable the swiotlb code to handle the cases where a device cannot directly
do DMA.  This is a complete rewrite of the Octeon DMA mapping code.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1639/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-10-29 19:08:32 +01:00
Roel Kluin
2fe0626080 MIPS: Cleanup switches with cases that can be merged 
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
To: linux-mips@linux-mips.org
To: Andrew Morton <akpm@linux-foundation.org>
To: LKML <linux-kernel@vger.kernel.org>
Patchwork: http://patchwork.linux-mips.org/patch/860/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-02-27 12:53:14 +01:00
David Daney
01a6221a6a MIPS: Reorganize Cavium OCTEON PCI support. 
Move the cavium PCI files to the arch/mips/pci directory.  Also cleanup
comment formatting and code layout.  Code from pci-common.c, was moved
into other files.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2009-07-03 15:45:29 +01:00
Renamed from arch/mips/cavium-octeon/pci.c (Browse further)