Still use i2c-gpio on boards which have a SoC with a TWI IP which
doesn't have clock stretching in transmission mode.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Add TWI nodes for atmel SoCs but keep i2c-gpio ones in order to let the
choice to the user in dts files.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
As indicated in the datasheet, TWD and TWCK must not be programmed as
open-drain.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nikolaus Voss <n.voss@weinmann.de>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
The G45 datasheets explicitly states that setting the open drain property
on peripheral function gpios is not allowed. (How about other A91 chips?)
Signed-off-by: Nikolaus Voss <n.voss@weinmann.de>
Tested-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
This driver has the following properties compared to the old driver:
1. Support for multiple interfaces.
2. Interrupt driven I/O as opposed to polling/busy waiting.
3. Support for _one_ repeated start (Sr) condition, which is enough
for most real-world applications including all SMBus transfer types.
(The hardware does not support issuing arbitrary Sr conditions on the
bus.)
testing: SoC: at91sam9g45
- BQ20Z80 battery SMBus client.
- on a 2.6.38 kernel with several i2c clients (temp-sensor,
audio-codec, touchscreen-controller, w1-bridge, io-expanders)
Signed-off-by: Nikolaus Voss <n.voss@weinmann.de>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Tested-by: Hubert Feurstein <h.feurstein@gmail.com>
Tested-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[wsa: squashed with the following patches from Ludovic to have some flaws
fixed:
i2c: at91: use managed resources
i2c: at91: add warning about transmission issues for some devices
i2c: at91: use an id table for SoC dependent parameters
]
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
It will get replaced by a superior one. Safe to remove since this one
depends on BROKEN anyhow.
Signed-off-by: Nikolaus Voss <n.voss@weinmann.de>
Tested-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[wsa: added commit message]
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
The old driver used con_id clock entries. Convert to use dev_id
for clock lookup via standard method.
Signed-off-by: Nikolaus Voss <n.voss@weinmann.de>
Tested-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
The ipu_di0 and ipu_di1 muxes referenced to nonexisting clocks. Use
ldb_di0_gate and ldb_di1_gate instead.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Platform dependant UART data refers to MX31 macro for MX35 machines.
For all other machines, macro usage matches machine type.
Though this compiles out to the same result, it looks much like
a typo, so fix it to use the right macros instead.
Signed-off-by: Oskar Schirmer <oskar@scara.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This also removes mach/clock.h along the way
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
The only code using mxc_decode_pll is clk-pllv1.c, so move the code
there.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Find and unwrap wrapped strings in the style:
pr_debug("clockdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", clkdm1->name, clkdm2->name);
Keeping these strings contiguous seems to be the current Linux kernel
policy.
The offending lines were found with the following command:
pcregrep -rnM '"\s*$\s*"' arch/arm/*omap*
While here, some messages have been clarified, some pr_warning(
... calls have been converted to pr_warn( ..., and some printk(KERN_*
... have been converted to pr_*.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Resolve the following warnings from smatch:
arch/arm/mach-omap2/gpmc.c:282 gpmc_cs_set_timings() info: why not propagate 'div' from gpmc_cs_calc_divider() instead of -1?
arch/arm/mach-omap2/serial.c:328 omap_serial_init_port() error: 'pdev' dereferencing possible ERR_PTR()
arch/arm/mach-omap2/timer.c:213 omap2_gp_clockevent_init() Error invalid range 4096 to -1
arch/arm/mach-omap2/gpio.c:63 omap2_gpio_dev_init() warn: possible memory leak of 'pdata'
arch/arm/mach-omap2/omap_hwmod.c:1478 _assert_hardreset() warn: assigning -22 to unsigned variable 'ret'
arch/arm/mach-omap2/omap_hwmod.c:1487 _assert_hardreset() warn: 4294963201 is more than 255 (max '(ret)' can be) so this is always the same.
arch/arm/mach-omap2/omap_hwmod.c:1545 _read_hardreset() warn: assigning -22 to unsigned variable 'ret'
arch/arm/mach-omap2/omap_hwmod.c:1554 _read_hardreset() warn: 4294963201 is more than 255 (max '(ret)' can be) so this is always the same.
arch/arm/mach-omap2/dpll3xxx.c:629 omap3_clkoutx2_recalc() error: we previously assumed 'pclk' could be null (see line 627)
arch/arm/mach-omap2/board-n8x0.c:422 n8x0_mmc_late_init() Error invalid range 14 to 13
arch/arm/mach-omap1/leds-h2p2-debug.c:71 h2p2_dbg_leds_event() error: potentially derefencing uninitialized 'fpga'.
arch/arm/plat-omap/mux.c:79 omap_cfg_reg() Error invalid range 4096 to -1
Thanks to Tony Lindgren <tony@atomide.com> for pointing out that BUG()
can be disabled. The changes in the first version that removed the
subsequent return() after BUG() states have been dropped.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
The prm44xx.o and sleep44xx.o build directives belong with the other
PRCM- and PM-related build sections in the Makefile; move them there.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Move MPU INTCPS (interrupt controller) and secure monitor code build
directives to their own Makefile sections, for clarity. Coalesce
SDRC-related Makefile directives into the SDRC Makefile section.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Move the omap_hwmod_common_data.o build directive down to the hwmod
data Makefile section where it belongs. Move the omap_hwmod.o build
directive to the top 'Common support' line, since we have no separate
hwmod code Makefile section, and it's currently needed for all OMAP2+.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch adds HWMOD data for all the peripherals of
AM335X device and also hooks up to the existing OMAP framework.
hwmod data has been already been cleaned up for the recent
changes in clocktree, where all leaf nodes have been removed,
since with modulemode based control, both clock and hwmod
interface does same thing. This reduces the code size to large
extent and also avoids duplication of same control.
So instead of specifying module's leaf node as a main_clk,
now we are relying on parent clock of module's functional clock.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: removed period in hwmod device names; changed mmc2 main_clk
to mmc_clk at Vaibhav's request; added trailing commas to structure
records at Tony's request to deal with some rmk parsing issues; added
OMAP_INTC_START to facilitate sparse-IRQ conversion]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
AM33XX PRCM architecture is different that any OMAP family
of devices, so it is required to have separate implementation
to handle AM33XX module enable/disable, reset assert/deassert
functionality.
This patch adds wrapper api's in omap_hwmod framework to
access prm/cm for AM33XX family of devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
[paul@pwsan.com: fixed checkpatch messages]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Here we have a bunch of miscellaneous cleanups and fixes
to the musb driver. It fixes a bunch of mistakes errors
which nobody has triggered before, so I'm not Ccing stable
tree.
We are finally improving OMAP's VBUS/ID Mailbox usage so
that we can introduce our PHY drivers properly. Also, we're
adding support for multiple instances of the MUSB IP in
the same SoC, as seen on some platforms from TI which
have 2 MUSB instances.
Other than that, we have some small fixes like not kicking
DMA for a zero byte transfer, or properly handling NAK timeout
on MUSB's host side, and the enabling of DMA Mode1 for any
transfers which are aligned to wMaxPacketSize.
All patches have been pending on mailing list for a long time
and I don't expect any big surprises with this pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQT1XLAAoJEIaOsuA1yqREsfMP/jae2huECuECrWtm76TNm6Kl
+1Movls2IkrYuVIM/QzSSqrmQ0BUVyOYjf1Uuke3tFA1KwkZsITZ12UONokiUGDd
EuPP0RfXSiwdVNWF6cyJ8PiT5JWXD2fRJn3L22pXSiA4MvocLXM0yJiHrsM5q3Hd
idg2npo7LEbLI3y1NDRdzR36Gk3y3K40U/ovXSQQQilhyk4yv7wpSbLqOR1UkkN/
Xcf2FiRb1xFYRdu1HoSHRnIW0CmC2a8MbpAcOuUSoPqH5HIiouA0Cc4Wt5xki4y3
+e0D0xpGK/Kt42nDkNoi51TaCw6aSY+GOqEFcI96o2/pq819nlcAzOGI77WGQIXX
sLud3oYsESdc++ux1+jaEX9xju41NyzColxDHn4AnplYF2t4fbTd36Loxed9xco/
LzHaaK3v1Ll30XiRiEnO5RBcgcwXDfFCMOUIDyVaVqNgCuYRrJIuhoXdlXvhEHAt
GQjFn/+8izIncVZ2rPQ1H2thshlmVWgrZ4kEwnbKLYtv2sqAVHBN/iaN25iQlm/l
Jva8ecXKl+9n92++X7vL8X/OmdVecBLey9eoqS+C+a0Kn9pSedOlUgkYpz8lGL38
dBPZ5Zjukl7J+gQ45ol5IN3cuYA+QcAZjHR1VEkeR7otAY5xsEun7vmyBoY4qazz
rUGhbofXB1gtGhUaaDBj
=UHPu
-----END PGP SIGNATURE-----
Merge tag 'musb-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
usb: musb: patches for v3.7 merge window
Here we have a bunch of miscellaneous cleanups and fixes
to the musb driver. It fixes a bunch of mistakes errors
which nobody has triggered before, so I'm not Ccing stable
tree.
We are finally improving OMAP's VBUS/ID Mailbox usage so
that we can introduce our PHY drivers properly. Also, we're
adding support for multiple instances of the MUSB IP in
the same SoC, as seen on some platforms from TI which
have 2 MUSB instances.
Other than that, we have some small fixes like not kicking
DMA for a zero byte transfer, or properly handling NAK timeout
on MUSB's host side, and the enabling of DMA Mode1 for any
transfers which are aligned to wMaxPacketSize.
All patches have been pending on mailing list for a long time
and I don't expect any big surprises with this pull request.
nop xceiv got its own header to avoid polluting otg.h. It has also
learned to work as USB2 and USB3 phys so we can use it on USB3
controllers.
Together with those two changes to nop xceiv, we're adding basic
PHY support to dwc3 driver, this is to allow platforms which actually
have a SW-controllable PHY talk to them through dwc3 driver.
We're adding a new phy driver for the OMAP architecture. This driver
is for the PHY found in OMAP4 SoCs, and a new phy driver for the
marvell architecture. An extra phy driver - for Tegra SoCs - is now
moving from arch/arm/mach-tegra* to drivers/usb/phy.
Also here, there's the creation of <linux/usb/phy.h> which should be
used from now on for PHY drivers, even those which don't support
OTG.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQThmRAAoJEIaOsuA1yqRE2U4P+gJHJsQZUIqTkCi6GyutMLUX
HUYVgaCXAbt4sSB5s0OK7AsB8uQ82GO6ZGyPfxNlYr6LXYlQWZ1OIig8PNhyn4en
lt0TolGL53fDOrwvQ0MIJBB1rgCk81UoFwJaPYkhKDNQLndl4hxlrFTsAvaIu7H0
pMMLt3E0Jz7018NxvVN23OV3EXnb2GF9K2Jt/NJNkZPanJaWXz0T/6DvBG24du2x
t3ALiKnpAC51wHPB5T88tefmVNApz7DPwK/Bm/VKW66LZ61Y+nZtZ+QMxj//uTt9
c3JXCvGscKSBcSfSFNMeYBdiPOZIFXTRVLr7CzxplvY9j5u8DTGArz5nvj/8ajbW
OeU0DMMaStfFqd12/BFUQeixbH8NUSoR5luWVMzBhB5+MF493gHvsu2ooorpR2hP
jQgMY146RdVbXNDJmuLRlVZbHQZfJBqvVUpk+3mdSSOtpy4IpKvlzPkYL1YjyOMt
x8WF+shSBvOMhg5C/HlGbDLzTiTv8zWef/aJ7OP9yUwYIz/map3lax749+M0Yzcj
trQgbLYrc8OeMVuCYGqjw1m96/YmcIxvzI/OnAMPbrPxK2hjy5jAu64/gOAZiZNY
oQis5G5qw/24LkXfLNQFTl8nYmaDko03+wazCg39D11bWZbLgKs9YJPZd78EwpJy
s+gU0+RYAQHgo+EChLY+
=/qVp
-----END PGP SIGNATURE-----
Merge tag 'xceiv-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
usb: xceiv: patches for v3.7 merge window
nop xceiv got its own header to avoid polluting otg.h. It has also
learned to work as USB2 and USB3 phys so we can use it on USB3
controllers.
Together with those two changes to nop xceiv, we're adding basic
PHY support to dwc3 driver, this is to allow platforms which actually
have a SW-controllable PHY talk to them through dwc3 driver.
We're adding a new phy driver for the OMAP architecture. This driver
is for the PHY found in OMAP4 SoCs, and a new phy driver for the
marvell architecture. An extra phy driver - for Tegra SoCs - is now
moving from arch/arm/mach-tegra* to drivers/usb/phy.
Also here, there's the creation of <linux/usb/phy.h> which should be
used from now on for PHY drivers, even those which don't support
OTG.
Removed:
* MACH_HARMONY
* MACH_PAZ00
* MACH_TRIMSLICE
These used to enable board support for individual boards. Now that we
only support device tree, these options have been removed.
Added:
* TEGRA_PCI
This used to be selected by the board options above. Select this
explicitly now that the board options have been removed.
* TEGRA_DEBUG_UART_AUTO_ODMDATA
This makes the kernel automatically pick a UART for earlyprintk. It's
likely to be a useful option for everyone.
* PWM
* PWM_TEGRA
Enable the new PWM subsystem, and the Tegra driver within it.
* GPIO_PCA953X
* GPIO_PCA953X_IRQ
* MFD_MAX8907
* REGULATOR_MAX8907
* RTC_DRV_MAX8907
* RTC_DRV_TPS65910
Various drivers required for the Whistler board.
* RTC_INTF_SYSFS
* RTC_INTF_PROC
* RTC_INTF_DEV
Some RTC options that Kconfig help implies should typically be
enabled.
* Wifi chip (rt3070)
* Bluetooth (btusb)
* Camera (uvcvideo)
* 3G modem (acm and wdm)
* rfkill
* GPIO LEDs
* NVEC
Various devices and features found on PAZ00 boards.
Some of these are enabled as modules because they are not needed for
boot and will not be used on other boards. Wifi also needs to be
module because of the firmware loader.
The update also enabled support for the rfkill switch, the Wifi LED and
the nvec power and led driver which got lost in the past.
* DEVTMPFS, TMPFS_POSIX_ACL
These are mandatory on modern linux distros.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
For Seaboard, Ventana, and Cardhu, add DT property to tell the regulator
that it should provide the pm_power_off() implementation. This allows
"shutdown" to work.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
When changing a PLL's rate, it must have no active children. The CPU
clock cannot be stopped, and CPU clock's divider is not used. The old
clock driver used to handle this by internally reparenting the CPU clock
onto a different PLL when changing the CPU clock rate. However, the new
common-clock based clock driver does not do this, and probably cannot do
this due to the locking issues it would cause.
To solve this, have the Tegra cpufreq driver explicitly perform the
reparenting operations itself. This is probably reasonable anyway,
since such reparenting is somewhat a matter of policy (e.g. which
alternate clock source to use, whether to leave the CPU clock a child
of the alternate clock source if it's running at the desired rate),
and hence is something more appropriate for the cpufreq driver than
the core clock driver anyway.
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000.
Use 64-bit math to prevent this.
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
It really becomes an maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.
Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx6q client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
SSI block has two types of clock:
ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.
Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.
Only register the ipg clock and do not register the peripheral clock for ssi.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: stable@vger.kernel.org
SSI block has two types of clock:
ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.
Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.
Only register the ipg clock and do not register the peripheral clock for ssi.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: stable@vger.kernel.org
The mailbox register for usb otg in omap is present in control module.
On detection of any events VBUS or ID, this register should be written
to send the notification to musb core.
Till we have a separate control module driver to write to control module,
omap2430 will handle the register writes to control module by itself. So
a new address space to represent this control module register is added
to usb_otg_hs.
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
'pinctrl_gpio_hog' is used to setup the pin functions, and it is not
neccesarily used only for GPIO pins, so remove 'gpio' from its name
to describe a more generic term.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Now, imx51 device tree kernel calls pinctrl to set up pins. The
function used to hook up non-DT pin setup is not needed for DT boot
any more. Remove it from DT image.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
With the imx51 DT board having pinctrl setup define in device tree,
it's time to remove dummy pinctrl state and build in the real imx51
pinctrl support.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Now imx53 is a device tree only platform, so the files and functions
used only by non-DT kernel can be removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
With device tree kernel provides the equal support as those imx53 board
files, it's time to remove the board files and get imx53 support device
tree only.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Now, imx53 device tree kernel calls pinctrl to set up pins. The
functions used to hook up non-DT pin setup is not needed for DT boot
any more. Remove them from DT image.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As all imx53 boards booting from device tree have pinctrl set up in dts,
it's time to remove the dummy pinctrl state and build in the real imx53
pinctrl support.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
