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24,942 commits

Author SHA1 Message Date
Josh Cartwright
6722df86ba ARM: 7570/1: quiet down the non make -s output
Commit edc88ceb0c silenced the make -s build, but
inadvertently made louder the non-silent build.  Fix by prepending '@' to each
of the added $(kecho) statements.

Build with edc88ceb0c:

  CHK     include/generated/compile.h
echo '  Kernel: arch/arm/boot/Image is ready'
  Kernel: arch/arm/boot/Image is ready
  LD      arch/arm/boot/compressed/vmlinux
  OBJCOPY arch/arm/boot/zImage
echo '  Kernel: arch/arm/boot/zImage is ready'
  Kernel: arch/arm/boot/zImage is ready

Build with this fix:
  CHK     include/generated/compile.h
  Kernel: arch/arm/boot/Image is ready
  LD      arch/arm/boot/compressed/vmlinux
  OBJCOPY arch/arm/boot/zImage
  Kernel: arch/arm/boot/zImage is ready

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-11-12 10:00:45 +00:00
Andrey Gusakov
9213c50d18 ARM: S3C64XX: Statically define parent clock of "camera" clock
The "camera" clock have only one parent. Define it statically and
remove unused source clock list.

Based on patch submitted by Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
(http://article.gmane.org/gmane.linux.kernel.samsung-soc/13691)

Signed-off-by: Andrey Gusakov <dron0gus@gmail.com>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-11-12 13:19:23 +09:00
Andrey Gusakov
9ffb571cb1 ARM: S3C64XX: Remove duplicated camera clock
Camera clock defined two times. One in init_clocks_off array with
"cam" name, second in clksrcs array with "camera" name. Leave
second definition because clock have divider.

Signed-off-by: Andrey Gusakov <dron0gus@gmail.com>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-11-12 13:08:11 +09:00
Greg Kroah-Hartman
f8b0655050 Merge 3.7-rc5 into staging-next 2012-11-11 18:28:26 -08:00
Gwenhael Goavec-Merou
ac8e44ced5 ARM: mxs: apf28dev: Add I2C and SPI support
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-12 10:07:43 +08:00
Greg Kroah-Hartman
7fd94beeca usb: gadget: patches for v3.8
renesas_usbhs implements ->pullup() method, switches over
 to devm_request_irq(), adds support for DMA Engine and
 got a few miscelaneous cleanups.
 
 The NCM gadget got an endianness fix and the Ethernet
 gadget a frame size fix.
 
 We're finally removing the g_file_storage gadget and
 sticking to g_mass_storage and the new tcm_usb_gadget
 gadgets since that was a huge duplicaton of effort anyway.
 
 While removing g_file_storage, we also had to fix a bunch
 of defconfigs which were still pointing to the old gadget.
 
 There's a big series getting us closer to being able to
 introduce our configfs interface. The series converts
 functions into loadable modules which will, eventually,
 be registered to the configfs interface.
 
 Other than that there's the usual typo fixes and miscelaneous
 cleanups all over the place.
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Merge tag 'gadget-for-v3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next

USB gadget patches from Felipe:
"usb: gadget: patches for v3.8

renesas_usbhs implements ->pullup() method, switches over
to devm_request_irq(), adds support for DMA Engine and
got a few miscelaneous cleanups.

The NCM gadget got an endianness fix and the Ethernet
gadget a frame size fix.

We're finally removing the g_file_storage gadget and
sticking to g_mass_storage and the new tcm_usb_gadget
gadgets since that was a huge duplicaton of effort anyway.

While removing g_file_storage, we also had to fix a bunch
of defconfigs which were still pointing to the old gadget.

There's a big series getting us closer to being able to
introduce our configfs interface. The series converts
functions into loadable modules which will, eventually,
be registered to the configfs interface.

Other than that there's the usual typo fixes and miscelaneous
cleanups all over the place."
2012-11-11 17:31:53 -08:00
Stanislav Meduna
67948adad1 ARM: mxs: Setup scheduler clock
Setup scheduler clock on ARM MXS platforms with a 32-bit timrot
such as i.MX28. This allows the scheduler to use sub-jiffy resolution.

The corresponding change for 16-bit v1 timrots is not possible
at the moment due to rounding issues with clock values wrapping
faster than once per several seconds in the common ARM platform code.

Signed-off-by: Stanislav Meduna <stano@meduna.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-12 09:27:30 +08:00
Linus Walleij
ae1cde8c50 Merge branch 'nomadik' into devel 2012-11-11 19:12:46 +01:00
Linus Walleij
e59d969f44 Merge branch 'at91' into devel 2012-11-11 19:12:33 +01:00
Viresh Kumar
4ddb1c2957 ARM: SPEAr: Add plgpio node in device tree dtsi files
This patch adds plgpio nodes in SPEAr DT files.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-11 19:08:52 +01:00
Linus Walleij
a6c45b99a6 pinctrl/coh901: use irqdomain, allocate irqdescs
This switches the COH 901 pinctrl driver to allocate its GPIO
IRQs dynamically, and start to use a linear irqdomain to map
from the hardware IRQs.

This way we can cut away the complex allocation of IRQ numbers
from the <mach/irqs.h> file.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-11 19:06:02 +01:00
Linus Walleij
d4a31ee899 ARM: U300: bump IRQs to offset 32
The U300 IRQs were bumped once to offset to 1 (in order to avoid
using IRQ 0 which is now NO_IRQ). This was OK as we were still
passing the number of irqs in the .nr_irqs field of the machine,
with descriptors allocated at boot time.

However .nr_irqs should be 0, leading the system to reserve the
first 16 IRQs. Then the VIC driver will complain that IRQs 1
thru 15 are pre-allocated, so to avoid this and use free
descriptors, move all IRQs up to offset 32.

This will all be done away with as we migrate to device tree,
so it is an interim solution.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-11 19:06:01 +01:00
David S. Miller
d4185bbf62 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
	drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

Minor conflict between the BCM_CNIC define removal in net-next
and a bug fix added to net.  Based upon a conflict resolution
patch posted by Stephen Rothwell.

Signed-off-by: David S. Miller <davem@davemloft.net>
2012-11-10 18:32:51 -05:00
Linus Torvalds
0020dd0b8c Bug-fixes:
* Fix compile issues on ARM.
  * Fix hypercall fallback code for old hypervisors.
  * Print out which HVM parameter failed if it fails.
  * Fix idle notifier call after irq_enter.
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Merge tag 'stable/for-linus-3.7-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen

Pull Xen fixes from Konrad Rzeszutek Wilk:
 "There are three ARM compile fixes (we forgot to export certain
  functions and if the drivers are built as an module - we go belly-up).

  There is also an mismatch of irq_enter() / exit_idle() calls sequence
  which were fixed some time ago in other piece of codes, but failed to
  appear in the Xen code.

  Lastly a fix for to help in the field with troubleshooting in case we
  cannot get the appropriate parameter and also fallback code when
  working with very old hypervisors."

Bug-fixes:
 - Fix compile issues on ARM.
 - Fix hypercall fallback code for old hypervisors.
 - Print out which HVM parameter failed if it fails.
 - Fix idle notifier call after irq_enter.

* tag 'stable/for-linus-3.7-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen:
  xen/arm: Fix compile errors when drivers are compiled as modules (export more).
  xen/arm: Fix compile errors when drivers are compiled as modules.
  xen/generic: Disable fallback build on ARM.
  xen/events: fix RCU warning, or Call idle notifier after irq_enter()
  xen/hvm: If we fail to fetch an HVM parameter print out which flag it is.
  xen/hypercall: fix hypercall fallback code for very old hypervisors
2012-11-10 06:56:21 +01:00
Ulf Hansson
50545e1d23 ARM: ux500: Remove cpufreq platform device
The cpufreq device is already added from the prcmu driver as
a mfd child device.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-09 16:42:39 -08:00
Tony Lindgren
edf8dde393 Merge branch 'linus' into omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3 2012-11-09 14:58:01 -08:00
Tony Lindgren
f56f52e02a Merge branch 'omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3' into omap-for-v3.8/dt
Conflicts:
	arch/arm/plat-omap/dmtimer.c

Resolved as suggested by Jon Hunter.
2012-11-09 14:54:17 -08:00
Tony Lindgren
84fbd2b8c8 Merge branch 'for_3.8/dts_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt into omap-for-v3.8/dt 2012-11-09 13:58:54 -08:00
Joseph Lo
ca3d241cb2 ARM: tegra: enable data prefetch on L2
Enable the data prefetch on L2. The bit28 in aux ctrl register.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2012-11-09 14:58:40 -07:00
Will Deacon
26ffd0d43b ARM: mm: introduce present, faulting entries for PAGE_NONE
PROT_NONE mappings apply the page protection attributes defined by _P000
which translate to PAGE_NONE for ARM. These attributes specify an XN,
RDONLY pte that is inaccessible to userspace. However, on kernels
configured without support for domains, such a pte *is* accessible to
the kernel and can be read via get_user, allowing tasks to read
PROT_NONE pages via syscalls such as read/write over a pipe.

This patch introduces a new software pte flag, L_PTE_NONE, that is set
to identify faulting, present entries.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 14:13:20 +00:00
Will Deacon
dbf62d5006 ARM: mm: introduce L_PTE_VALID for page table entries
For long-descriptor translation table formats, the ARMv7 architecture
defines the last two bits of the second- and third-level descriptors to
be:

	x0b	- Invalid
	01b	- Block (second-level), Reserved (third-level)
	11b	- Table (second-level), Page (third-level)

This allows us to define L_PTE_PRESENT as (3 << 0) and use this value to
create ptes directly. However, when determining whether a given pte
value is present in the low-level page table accessors, we only need to
check the least significant bit of the descriptor, allowing us to write
faulting, present entries which are required for PROT_NONE mappings.

This patch introduces L_PTE_VALID, which can be used to test whether a
pte should fault, and updates the low-level page table accessors
accordingly.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 14:13:19 +00:00
Will Deacon
0cbbbad631 ARM: mm: don't use the access flag permissions mechanism for classic MMU
The simplified access permissions model is not used for the classic MMU
translation regime, so ensure that it is turned off in the sctlr prior
to turning on address translation for ARMv7.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 14:13:19 +00:00
Will Deacon
864aa04cd0 ARM: mm: use pteval_t to represent page protection values
When updating the page protection map after calculating the user_pgprot
value, the base protection map is temporarily stored in an unsigned long
type, causing truncation of the protection bits when LPAE is enabled.
This effectively means that calls to mprotect() will corrupt the upper
page attributes, clearing the XN bit unconditionally.

This patch uses pteval_t to store the intermediate protection values,
preserving the upper bits for 64-bit descriptors.

Cc: stable@vger.kernel.org
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 14:12:55 +00:00
Stefano Stabellini
ab277bbf66 xen/arm: Fix compile errors when drivers are compiled as modules (export more).
The commit 911dec0db4
"xen/arm: Fix compile errors when drivers are compiled as modules." exports
the neccessary functions. But to guard ourselves against out-of-tree modules
and future drivers hitting this, lets export all of the relevant
hypercalls.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2012-11-09 07:48:22 -05:00
Afzal Mohammed
47acde1672 ARM: OMAP2+: tusb6010: generic timing calculation
Generic gpmc timing calculation helper is available now, use
it instead of custom timing calculation.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
2012-11-09 18:07:23 +05:30
Afzal Mohammed
ac2d9ae194 ARM: OMAP2+: smc91x: generic timing calculation
Generic gpmc timing calculation helper is available now, use
it instead of custom timing calculation.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
2012-11-09 18:07:22 +05:30
Afzal Mohammed
4f4426f900 ARM: OMAP2+: onenand: generic timing calculation
Generic gpmc timing calculation helper is available now, use
it instead of custom timing calculation.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
2012-11-09 18:07:12 +05:30
Afzal Mohammed
246da26d37 ARM: OMAP2+: gpmc: generic timing calculation
Presently there are three peripherals that gets it timing
by runtime calculation. Those peripherals can work with
frequency scaling that affects gpmc clock. But timing
calculation for them are in different ways.

Here a generic runtime calculation method is proposed. Input
to this function were selected so that they represent timing
variables that are present in peripheral datasheets. Motive
behind this was to achieve DT bindings for the inputs as is.
Even though a few of the tusb6010 timings could not be made
directly related to timings normally found on peripherals,
expressions used were translated to those that could be
justified.

There are possibilities of improving the calculations, like
calculating timing for read & write operations in a more
similar way. Expressions derived here were tested for async
onenand on omap3evm (as vanilla Kernel does not have omap3evm
onenand support, local patch was used). Other peripherals,
tusb6010, smc91x calculations were validated by simulating
on omap3evm.

Regarding "we_on" for onenand async, it was found that even
for muxed address/data, it need not be greater than
"adv_wr_off", but rather could be derived from write setup
time for peripheral from start of access time, hence would
more be in line with peripheral timings. With this method
it was working fine. If it is required in some cases to
have "we_on" same as "wr_data_mux_bus" (i.e. greater than
"adv_wr_off"), another variable could be added to indicate
it. But such a requirement is not expected though.

It has been observed that "adv_rd_off" & "adv_wr_off" are
currently calculated by adding an offset over "oe_on" and
"we_on" respectively in the case of smc91x. But peripheral
datasheet does not specify so and so "adv_rd(wr)_off" has
been derived (to be specific, made ignorant of "oe_on" and
"we_on") observing datasheet rather than adding an offset.
Hence this generic routine is expected to work for smc91x
(91C96 RX51 board). This was verified on smsc911x (9220 on
OMAP3EVM) - a similar ethernet controller.

Timings are calculated in ps to prevent rounding errors and
converted to ns at final stage so that these values can be
directly fed to gpmc_cs_set_timings(). gpmc_cs_set_timings()
would be modified to take ps once all custom timing routines
are replaced by the generic routine, at the same time
generic timing routine would be modified to provide timings
in ps. struct gpmc_timings field types are upgraded from
u16 => u32 so that it can hold ps values.

Whole of this exercise is being done to achieve driver and
DT conversion. If timings could not be calculated in a
peripheral agnostic way, either gpmc driver would have to
be peripheral gnostic or a wrapper arrangement over gpmc
driver would be required.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
2012-11-09 18:07:11 +05:30
Afzal Mohammed
559d94b00c ARM: OMAP2+: gpmc: handle additional timings
Configure busturnaround, cycle2cycledelay, waitmonitoringtime,
clkactivationtime in gpmc_cs_set_timings(). This is done so
that boards can configure these parameters of gpmc in Kernel
instead of relying on bootloader. Also configure bool type
timings like extradelay.

This needed change to the existing users that were configuring
clk activation time and extra delay by directly writing to
registers. Thanks to Tony for making me aware of users of clk
activation and being kind enough to test the modified one.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
2012-11-09 18:07:11 +05:30
Will Deacon
f435ab7992 ARM: hw_breakpoint: kill WARN_ONCE usage
WARN_ONCE is a bit OTT for some of the simple failure cases encountered
in hw_breakpoint, so use either pr_warning or pr_warn_once instead.

Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:47:06 +00:00
Dietmar Eggemann
9e962f7660 ARM: hw_breakpoint: use CRn as argument for debug reg accessor macros
The coprocessor register CRn for accesses to the debug register can be a
different one than C0. Take this into account for the ARM_DBG_READ and
the ARM_DBG_WRITE macro.

The inline assembler calls which used a coprocessor register CRn other
than C0 are replaced by the ARM_DBG_READ or ARM_DBG_WRITE macro.

Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:47:06 +00:00
Will Deacon
0daa034e69 ARM: hw_breakpoint: check if monitor mode is enabled during validation
Rather than attempt to enable monitor mode explicitly when scheduling in
a breakpoint event (which could raise an undefined exception trap when
accessing DBGDSCRext), instead check that DBGDSCRint.MDBGen is set
during event validation and report an error to the caller if not.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:47:06 +00:00
Will Deacon
5ad29ea24e ARM: hw_breakpoint: make boot quieter without CPUID feature registers
Booting on a v6 core without the CPUID feature registers (e.g. 1136)
leads to a noisy dmesg complaining about their absence.

This patch changes the pr_warning into a pr_warn_once to keep the log
quieter.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:47:06 +00:00
Will Deacon
7f4050a07b ARM: hw_breakpoint: don't try to clear v6 debug registers during boot
v6 cores do not provide a way to clear the debug registers without first
enabling monitor mode, meaning that we could take spurious debug
exceptions. Instead, rely on the registers being in a sane state when we
boot as they are defined to be disabled out of reset anyway.

Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:47:06 +00:00
Will Deacon
614bea500a ARM: hw_breakpoint: fix ordering of debug register reset sequence
The debug register reset sequence for v7 and v7.1 is congruent with
tap-dancing through a minefield.

Rather than wait until we've blown ourselves to pieces, this patch
instead checks the debug_err_mask after each potentially faulting
operation. We also move the enabling of monitor_mode to the end of the
sequence in order to prevent spurious debug events generated by UNKNOWN
register values.

Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:47:06 +00:00
Will Deacon
b59a540ca9 ARM: hw_breakpoint: fix monitor mode detection with v7.1
Detecting whether halting debug is enabled is no longer possible via
the DBGDSCR in v7.1, returning an UNKNOWN value for the HDBGen bit via
CP14 when the OS lock is clear.

This patch removes the halting mode check and ensures that accesses to
the internal and external views of the DBGDSCR are serialised with an
instruction barrier.

Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:47:05 +00:00
Will Deacon
e64877dcf5 ARM: hw_breakpoint: only clear OS lock when implemented on v7
The OS save and restore register are optional in debug architecture v7,
so check the status register before attempting to clear the OS lock.

Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:47:05 +00:00
Jon Hunter
2ac29a14a8 ARM: PMU: fix runtime PM enable
Commit 7be2958 (ARM: PMU: Add runtime PM Support) updated the ARM PMU code to
use runtime PM which was prototyped and validated on the OMAP devices. In this
commit, there is no call pm_runtime_enable() and for OMAP devices
pm_runtime_enable() is currently being called from the OMAP PMU code when the
PMU device is created. However, there are two problems with this:

1. For any other ARM device wishing to use runtime PM for PMU they will need
   to call pm_runtime_enable() for runtime PM to work.
2. When booting with device-tree and using device-tree to create the PMU
   device, pm_runtime_enable() needs to be called from within the ARM PERF
   driver as we are no longer calling any device specific code to create the
   device. Hence, PMU does not work on OMAP devices that use the runtime PM
   callbacks when using device-tree to create the PMU device.

Therefore,  call pm_runtime_enable() directly from the ARM PMU driver when
registering the device. For platforms that do not use runtime PM,
pm_runtime_enable() does nothing and for platforms that do use runtime PM but
may not require it specifically for PMU, this will just add a little overhead
when initialising and uninitialising the PMU device.

Tested with PERF on OMAP2420, OMAP3430 and OMAP4460.

Acked-by: Kevin Hilman <khilman@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:37:26 +00:00
Will Deacon
0305230a3d ARM: perf: consistently use arm_pmu->name for PMU name
Perf has three ways to name a PMU: either by passing an explicit char *,
reading arm_pmu->name or accessing arm_pmu->pmu.name.

Just use arm_pmu->name consistently in the ARM backend.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:37:26 +00:00
Will Deacon
288700d16d ARM: perf: return NOTIFY_DONE from cpu notifier when no available PMU
When attempting to reset the PMU state for either a NULL PMU or a PMU
implementation without a reset function, return NOTIFY_DONE from the CPU
notifier as we don't care about the hotplug event.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:37:26 +00:00
Mark Rutland
2a4961ba89 ARM: perf: register cpu_notifier at driver init
The current practice of registering the cpu hotplug notifier at PMU
registration time won't be safe with multiple PMUs, as we'll repeatedly
attempt to register the notifier. This has the unfortunate effect of
silently corrupting the notifier list, leading to boot stalling.

Instead, register the notifier at init time. Its sanity checks will
prevent anything bad from happening if the notifier is called before we
have any PMUs registered.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:37:25 +00:00
Sudeep KarkadaNagesha
7279adbd9b ARM: perf: check ARMv7 counter validity on a per-pmu basis
Multi-cluster ARMv7 systems may have CPU PMUs with different number of
counters.

This patch updates armv7_pmnc_counter_valid so that it takes a pmu
argument and checks the counter validity against that. We also remove a
number of redundant counter checks whether the current PMU is not easily
retrievable.

Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:37:25 +00:00
Sudeep KarkadaNagesha
ed6f2a5223 ARM: perf: consistently use struct perf_event in arm_pmu functions
The arm_pmu functions have wildly varied parameters which can often be
derived from struct perf_event.

This patch changes the arm_pmu function prototypes so that struct
perf_event pointers are passed in preference to fields that can be
derived from the event.

Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:37:25 +00:00
Sudeep KarkadaNagesha
513c99ce4e ARM: perf: allocate CPU PMU dynamically at probe time
Supporting multiple, heterogeneous CPU PMUs requires us to allocate the
arm_pmu structures dynamically as the devices are probed.

This patch removes the static structure definitions for each CPU PMU
type and instead passes pointers to the PMU-specific init functions.

Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:37:25 +00:00
Marc Zyngier
e50c54189f ARM: perf: add guest vs host discrimination
Add minimal guest support to perf, so it can distinguish whether
the PMU interrupt was in the host or the guest, as well as collecting
some very basic information (guest PC, user vs kernel mode).

This is not feature complete though, as it doesn't support backtracing
in the guest.

Based on the x86 implementation, tested with KVM/ARM.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2012-11-09 11:37:24 +00:00
Tomasz Figa
75e56c98ef ARM: EXYNOS: Add missing USB regulators for origen
This patch adds missing USB OTG regulators needed for s3c-hsotg driver
to work on Origen board.

Confirmed with schematics of and tested on Origen board.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-11-09 15:10:29 +09:00
Paul Walmsley
b99db36cdf ARM: OMAP2+: PRCM: remove obsolete prcm.[ch]
arch/arm/mach-omap2/prcm.c and arch/arm/plat-omap/include/plat/prcm.h
are now completely unused and can be removed.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
2012-11-08 15:09:26 -07:00
Paul Walmsley
2577a4a609 ARM: OMAP2+: hwmod: call to _omap4_disable_module() should use the SoC-specific call
The hwmod code unconditionally calls _omap4_disable_module() on all
SoCs when a module doesn't enable correctly.  This "worked" due to the
weak function omap4_cminst_wait_module_idle() in
arch/arm/mach-omap2/prcm.c, which was a no-op.  But now those weak
functions are going away - they should not be used.  So this patch
will now call the SoC-specific disable_module code, assuming it
exists.

Needs to be done before the weak function is removed, otherwise AM33xx
will crash early in boot.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
2012-11-08 15:09:26 -07:00
Paul Walmsley
b13159afb4 ARM: OMAP2+: PRCM: consolidate PRCM-related timeout macros
Consolidate all of the copies of MAX_MODULE_HARDRESET_WAIT and
MAX_MODULE_SOFTRESET_WAIT into one place, arch/arm/mach-omap2/prm.h.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
2012-11-08 15:09:26 -07:00
Paul Walmsley
d9a16f9ab9 ARM: OMAP2+: PRCM: split and relocate the PRM/CM globals setup
Split omap2_set_globals_prcm() into PRM, CM, and PRCM_MPU variants, since
these are all separate IP blocks.  This should make it easier to move the
PRM, CM, PRCM_MPU code into drivers/ in future patchsets.

At this point arch/arm/plat-omap/include/plat/prcm.h is empty; a
subsequent patch will remove it, and remove the #include from all the
files that #include it.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
2012-11-08 15:09:26 -07:00