For the SAMA5D4 SoC, some LCD lines are in conflict with useful peripherals.
Remove these lines and the lowest significant bit of a 24 bit LCD. It gives
us a RGB 777 configuration.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The color arrangement for SAMA5D4 in RGB 666 takes the most significant bits of
each color line groups.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs
(i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Anthony Harivel <anthony.harivel@emtrion.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define alternative pin muxing for the LCDC pins.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Anthony Harivel <anthony.harivel@emtrion.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The HLCDC (HLCD Controller) IP supports 4 different output mode (RGB444,
RGB565, RGB666 and RGB888) and the pin muxing will depend on the chosen
RGB mode.
Split pin definitions to be able to set pin config according to the
selected mode.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Anthony Harivel <anthony.harivel@emtrion.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Conflicts:
drivers/net/ethernet/emulex/benet/be_main.c
net/core/sysctl_net_core.c
net/ipv4/inet_diag.c
The be_main.c conflict resolution was really tricky. The conflict
hunks generated by GIT were very unhelpful, to say the least. It
split functions in half and moved them around, when the real actual
conflict only existed solely inside of one function, that being
be_map_pci_bars().
So instead, to resolve this, I checked out be_main.c from the top
of net-next, then I applied the be_main.c changes from 'net' since
the last time I merged. And this worked beautifully.
The inet_diag.c and sysctl_net_core.c conflicts were simple
overlapping changes, and were easily to resolve.
Signed-off-by: David S. Miller <davem@davemloft.net>
Update dts file to reflect:-
* new flash memory layout
* add missing phy-mode property
* dual_emac now just a boolean
* rename mcp to microchip
* update gpio definition
Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for the primary camera of the Nokia N950 and N9.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The resources the ISP needs are slightly different on 3[45]xx and 3[67]xx.
Especially the phy-type property is different.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[tony@atomide.com: use omap3_scm_general instead of scm_conf for now]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This L2 controller handles multiplexing a few different interrupts. We
also need it for configuring the interrupt forwarding masks for the
UART.
With this, we can *now* boot BCM7445 to a prompt using the upstream
kernel + DTB.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
These files are not used by any DTS file anymore.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This value makes much more sense in decimal.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Gregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch just move content of file omap34xx-hs.dtsi into omap3-tao3530.dts.
There is no code change, patch is just preparation for removing -hs file.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch moves content of file omap34xx-hs.dtsi into omap3-n900.dts and enable
omap sham support (omap HW support for SHA + MD5). After testing both omap hwmod
and omap-sham.ko drivers it looks like signed Nokia X-Loader enable L3 firewall
for omap sham. There is no kernel crash with both official bootloader and crypto
enable bootloader. So we can safely enable sham code.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Harmattan system on Nokia N9 and N950 devices uses omap crypto support.
Bootloader on those devices is known that it enables HW crypto support.
This patch just include omap36xx.dtsi directly, so aes and sham is enabled.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On dm816x we have no PIN_INPUT vs PIN_OUTPUT configuration, there
are just pulls. Let's remove the bogus flags.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Looks like we have cppi41 on dm816x just like on am335x.
Cc: Bin Liu <binmlist@gmail.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit a54879a008 ("ARM: dts: Fix USB dts configuration for dm816x")
attempted to fix the USB features introduced by commit 7800064ba5
("ARM: dts: Add basic dm816x device tree configuration") but obviously
I did not read the dmesg as more USB issues still keep trickling in.
It should be usb1_pins instead not usb0_pins for the second interface
to avoid warnings from pinctrl framework.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1
Trying to use the master without this change results in the kernel boot
process waiting forever for an interrupt that will never occur while
attempting to probe any slave devices configured in the device tree as being
under SPI master 1.
The change works for the Cyclone V, and according to the Arria 5 handbook
should be good there too.
Signed-off-by: Mark James <maj@jamers.net>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
For L2 cache controller node, cache-level property is mandatory. Let's
add it to Armada 370 and Armada XP device tree.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The resources of the cpuclk node are overlapping the one from
coredivclk node. It was not noticed until now because the driver did a
simple of_iomap and not a request_mem_region. This patch fixes it.
[gregory.clement@free-electrons.com: add commit log and port to 4.0-rc]
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Commit 7800064ba5 ("ARM: dts: Add basic dm816x device tree
configuration") added basic devices for dm816x, but I was not able
to test the GPIO interrupts earlier until I found some suitable pins
to test with. We can mux the MMC card detect and write protect pins
from SD_SDCD and SD_SDWP mode to use a normal GPIO interrupts that
are also suitable for the MMC subsystem.
This turned out several issues that need to be fixed:
- I set the GPIO type wrong to be compatible with omap3 instead
of omap4. The GPIO controller on dm816x has EOI interrupt
register like omap4 and am335x.
- I got the GPIO interrupt numbers wrong as each bank has two
and we only use one. They need to be set up the same way as
on am335x.
- The gpio banks are missing interrupt controller related
properties.
With these changes the GPIO interrupts can be used with the
MMC card detect pin, so let's wire that up. Let's also mux all
the MMC lines for completeness while at it.
For the first GPIO bank I tested using GPMC lines temporarily
muxed to GPIOs on the dip switch 10.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now that we don't have hwmod entry for pcie PHY remove the
ti,hwmod property from PCIE PHY's. Otherwise we will get:
platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[tony@atomide.com: updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the PMU block is actually the first
interrupt controller in the chain for RTC, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs may not even boot.
Also, I strongly suspect that there is more than two wake-up
interrupts on these platforms, but I leave it to the maintainers
to fix their mess.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1426088693-15724-2-git-send-email-marc.zyngier@arm.com
[ jac: squash in maz's fixup from
https://lkml.kernel.org/r/5506989D.9050703@arm.com ]
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 385 AP board has a USB3 port exposed that uses a GPIO to drive the
VBUS line. Enable the needed drivers to support this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Now that we have EXTCON_USB_GPIO queued for v4.1, revert
commit addfcde7c4 ("ARM: dts: dra7x-evm: beagle-x15: Fix USB Host")
On these EVMs, the USB cable state has to be determined via the
ID pin tied to a GPIO line. We use the gpio-usb-extcon driver
to read the ID pin and the extcon framework to forward
the USB cable state information to the USB driver so the
controller can be configured in the right mode (host/peripheral).
Gets USB peripheral mode to work on this EVM.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Both GSCALER IPs in gsc power domain have async-bridges (to FIMD and MIXER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Configure the pins in external interrupt mode, as done for Snow in
e5e5c6d14e ("ARM: dts: Add power and lid GPIO keys pinctrl for
exynos5250-snow").
Reported-by: Kukjin Kim <kgene@kernel.org>
Suggested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Fixes: 53dd4138bb ("ARM: dts: Add exynos5250-spring device tree")
Signed-off-by: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Resolve a merge conflict with mmc refactoring aaa25a5a33 ("ARM: dts:
unuse the slot-node and deprecate the supports-highspeed for dw-mmc in
exynos") by dropping the slot@0 nodes, moving its bus-width property to
the mmc node and replacing supports-highspeed with cap-{mmc,sd}-highspeed,
matching exynos5250-snow.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Fixes: 53dd4138bb ("ARM: dts: Add exynos5250-spring device tree")
Signed-off-by: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: <stable@vger.kernel.org> [3.19+]
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The kernel can use as the default console a serial port if is defined
as stdout device in the Device Tree.
This allows a board to be booted without the need of having a console
parameter in the kernel command line.
Currently the Spring DTS has bootargs in the /chosen node and this is
kept since users that don't have a serial console on this board might
be using it to have the boot log shown in the display. This will have
more precedence than the stdout-path but it's fine since is only used
when CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is enabled.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The kernel can use as the default console a serial port if is defined
as stdout device in the Device Tree.
This allows a board to be booted without the need of having a console
parameter in the kernel command line.
Currently the Snow DTS has a bootargs in the /chosen node and this is
kept since users that don't have a serial console on this board might
be using it to have the boot log shown in the display. This will have
more precedence than the stdout-path but it's fine since is only used
when CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is enabled.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The kernel can use as the default console a serial port if is defined
as stdout device in the Device Tree.
This allows a board to be booted without the need of having a console
parameter in the kernel command line.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Use assigned-clocks/assigned-clock-parents properties for
CMU clock controller DT node to secure proper clock setup:
switching the two muxes to root oscillator clock is not only
required for proper powering down the ISP power domain,
but it also reduces the risk of accessing the ISP CMU
registers while the ISP power domain remains turned off
(i.e. through the common clock framework by clk_summary)
Signed-off-by: Beata Michalska <b.michalska@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
The Armada 380 and 385 SoCs have a Cortex-A9 CPU, so the PMU is available
to be used. This commit enables it in the devicetree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 375 SoC has a Cortex-A9 CPU, and so the PMU is available
to be used. This commit enables it in the devicetree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 370 and XP SoCs have Cortex-A9 compatible CPUs, and with a
Performance Monitoring Unit.
Enable it so that we can have hardware-assisted perf support.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Remove the 'ti,timer-dsp' and 'ti,timer-pwm' properties from the timer
nodes that still have them. This seems to be copied from OMAP5, on
which only certain timers are capable of providing PWM functionality
or be able to interrupt the DSP. All the GPTimers On DRA7 are capable
of PWM and interrupting any core (due to the presence of Crossbar).
These properties were used by the driver to add capabilities to each
timer, and support requesting timers by capability. In the DT world,
we expect any users of timers to use phandles to the respective timer,
and use the omap_dm_timer_request_by_node() API. The API to request
using capabilities, omap_dm_timer_request_by_cap() API should be
deprecated eventually.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ti,codec property is not used (parsed) in omap-twl4030 driver. The ti,twl4030-audio
which ti,codec points by phandle is mfd driver and device for ASoC codec is created
w/o DT compatible string. Removing all references in DT files.
Signed-off-by: Marek Belisko <marek@goldelico.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The beagle board contains a 16-bit NAND device connected to
chip select 0 of the GPMC controller.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch updates hdq node compatible property to "ti,am4372-hdq".
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Added Pandora 1 GHz model which is based on Classic/Rebirth
with following changes:
- upgraded cpu to dm3730 runs on 1GHz
- 512 MiB DDR-333 SDRAM @ 200 MHz
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Added Pandora Rebirth model which is based on Pandora
Classic with 512 MiB DDR-333 SDRAM memory.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
