For ccm clock gate, both 2b'11 and 2b'01 should be treated
as clock enabled, see below description in CCM, whenver CPU
trys to check clock gate's status, system will be in run mode.
2b'00: clock is off during all modes;
2b'01: clock is on in run mode, but off in wait and stop mode;
2b'10: Not applicable;
2b'11: clock is on during all modes, except stop mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Common clk framework will disable unused clks in late init only if
they are enabled by default and no one is using it, so we need to
add is_enabled callback for clk framework to get clks' status.
PFD clocks are enabled by hardware reset, so we need to add
interface for common clk framework to disable those unused ones for
saving power.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
PFUZE100 regulator is commonly found on mx6 based designs.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Let MX35 and MX50 device tree support be built by default.
Generated by doing:
- Selected CONFIG_MACH_IMX35_DT and CONFIG_SOC_IMX50 via 'make menuconfig'
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Update the IMX v6/v7 defconfig for the SolidRun HummingBoard:
- Add AT803X ethernet phy
- Add consumer IR devices
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We are missing spba clock in imx6sl's clock tree, thus add it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
0-DAY kernel build testing backend reports the following.
scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
# many are suggestions rather than must-fix
ERROR: Use of const init definition must use __initconst
#80: arch/arm/mach-imx/mach-imx50.c:26:
+static const char *imx50_dt_board_compat[] __initdata = {
While at it, fix the error globally for IMX platform.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE,
thus the DI0 interface will be turned off inadvertently during boot.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.
In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
According to the i.MX50 Rev. 1 and i.MX53 Rev. 2.1 datasheet the lp_apm_sel is
bit 10 in the CCM_CCSR register not bit 9. On the i.MX51 it's bit 9.
This patch fixes this issue.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Linux-IDE <linux-ide@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of selecting PINCTRL on individual SoC, let's select it at IMX
sub-architecure level.
While at it, it also adds the missing PINCTRL_IMX50 selection for
SOC_IMX50.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use clock defines in order to make devicetrees more
human readable.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Due to incorrect clock specified in MDMA0 node, using MDMA0 controller
could cause system failures, due to wrong clock being controlled. This
patch fixes this by specifying correct clock.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Corrected commit message and description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
The chosen nodes are nowadays pretty useless, since they will be overriden by
the bootloader anyway.
We can thus safely remove them.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner sunXi SoCs DT changes for clocks
This contains the DT parts of the "[PATCH v3 00/13] clk: sunxi: add PLL5
and PLL6 support" series. It adds DT nodes for PLL4/5/6 and mod0 clocks
on most sunxi platforms.
* r7s72100 SoC (RZ/A1H) based Genmai Board
- Fixup I2C device on defconfig
- Add gpio regulator support on defconfig
* r8a7791 (R-Car M2) based Koelsch board
- Do not disable CONFIG_{INOTIFY_USER,UNIX} in defconfig
- Enable CONFIG_PACKET in defconfig
- Enable Ether in defconfig
* r8a7740 (R-Mobile A1) based Armadillo board
- Enable backlight control in defconfig
* r8a7740 (R-Mobile A1) based Armadillo board
- Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSuP0OAAoJENfPZGlqN0++MhsP/iV7i5qhbzKV6oPVFlBjpgMk
cp/6KikJ/9e5Nz8nGd1Q3n22/Vkw+U2JYQ0wkofJerO4AEm/Ikwf1FSRlDG4l1OR
q4/a8/ajIkZaExiztXQgwN73AyAE0vo8TWq+7qRlz6pmar8F3q32Lp1PwS7qK5zJ
NfK/JkiYJ0wH1X9Z3l3oHvKKZtoveTBYUyP/wYyfipbmesumpytWESQHWvANm0LQ
WL5haaT2F0auDLkMxnb9yIx+334oVDeRIyD/iDb3pu5OvA2Q1Xa5xWrnRYXSkOpq
UfylrS2N5LEs2teHfHiU2Rce7PDtml5TDv+uORrqMd/l76+huJYmxZcMK88NepGb
Si5Zl2GTdueAwdS1B0qdDQvkz7RYeETVwBagtQ16P6bWPbExivtqJa4zhdlm43jM
tGvU6MVv5nrqgPLUOoFRJuwutU3mIQ8+36i+MMKnePjoEvG2iCgb/X/F5x2M3Cag
xs6hsLlAkNOC/yr2A5DABzb3FPjhKvEjy0yNJFmJ0pyiHcUKuxO4HPEh74Dp0TTm
q3UHLkjXBQf5IZo0U7qUuFL+rjz6u3EbvOgddfPnPCMKJIdEWe6OtYK2N2X+BFTJ
g1tGWA2PeyO7XrNzEJ2Z5x10VTGjWywgAHRVmdBXJd0kIOARYdXRqB0Vy+M7LwKL
5mjeK9mRR3u1Lbouuzs3
=M9DB
-----END PGP SIGNATURE-----
Merge tag 'renesas-defconfig2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards
From Simon Horman:
Second Round of Renesas ARM Based SoC Defconfig Updates for v3.14
* r7s72100 SoC (RZ/A1H) based Genmai Board
- Fixup I2C device on defconfig
- Add gpio regulator support on defconfig
* r8a7791 (R-Car M2) based Koelsch board
- Do not disable CONFIG_{INOTIFY_USER,UNIX} in defconfig
- Enable CONFIG_PACKET in defconfig
- Enable Ether in defconfig
* r8a7740 (R-Mobile A1) based Armadillo board
- Enable backlight control in defconfig
* r8a7740 (R-Mobile A1) based Armadillo board
- Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY
* tag 'renesas-defconfig2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: koelsch: Do not disable CONFIG_{INOTIFY_USER,UNIX} in defconfig
ARM: shmobile: koelsch: Enable CONFIG_PACKET in defconfig
ARM: shmobile: armadillo800eva: Enable backlight control in defconfig
ARM: shmobile: Koelsch: enable Ether in defconfig
ARM: shmobile: genmai: Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY
ARM: shmobile: lager: fixup I2C device on defconfig
ARM: shmobile: lager: add gpio regulator support on defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
* Global
- Kconfig: Mention Renesas ARM SoCs instead of SH-Mobile
* r7s72100 SoC (RZ/A1H) based Genmai Board
- Add Multiplatform support
- Add Reference DT
* r8a7791 (R-Car M2) based Koelsch board
- Add pinctrl_register_mappings() for Koelsch
- Hook up SW30-SW36 on Koelsch
- Mark GPIO keys as wake-up sources
- Use ->init_late()
- Add Multiplatform support
- Set .debounce_interval for GPIO keys
- Add SW2 to GPIO keys
- Add Led 6, 7 and 8 support
- Add reference DT
- Enable PFC/GPIO
* r8a7790 (R-Car H2) based Lager board
- Add gpio/fixed regulator for SDHI
- Add SPI FLASH support on QSPI
- Mark GPIO keys as wake-up sources
- Use ->init_late()
- Set .debounce_interval for GPIO keys
* r8a7778 (R-Car M1) based Bock-W board
- bockw: remove unused RSND_SSI_CLK_FROM_ADG
- Set .debounce_interval for GPIO keys
- Correct FPGA ioremap area
- Use regulator for MMCIF
* r8a7740 (R-Mobile A1) based Armadillo board
- Correct FSI address size
* sh7374 (SH-Mobile AP4) based Mackerel board
- Use pinconf API to configure pin pull-down
- clk_round_rate() can return a zero to indicate an error
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSt5cHAAoJENfPZGlqN0++xIoP/jBunLyY+xAZ+06gukAdKEw4
hLoUH55GsvpaL5cuDT+LSXWafIol4A/wvME5sZJsKoCHRnDqQYKvyE7hDLIlvLRI
KvcmFvdUcN6plbD/wz/SPzur/Lq3+DcX4ep8pmI7OUXupYWomibwylv/5UgY++PN
Uymmre4CiHK7/wzWOyS79ujcGzdwk4o1ari5P2lC4fUlVM7jZ7DQswglo+jGxscw
CXHtEfqto4NEh2+05sAGdmRHwb3xwOndPYwHaFWy+X6uce/BZXsgDipWihHI5ZKr
FT+TemFlYwXc2In2F/E4T7aXqNDXSjEcX/x2/VHS5W2EoWbSk+Mz6zlFZduAv4oG
c35AQjHMktlo6voZm0L4WgH0JYT4dyu6DJG3mo7adRyYKvjv/OC48wt4jhYa0LGZ
XLcYBoaK1zqpG2M6ZIv138a9krGtkfSCy/Pt7YQ4WpA8CQyJlYqaoW9Yrpkhw13b
OcO22myGbjMnxTwpqS9rwDPnNR2PjG9ExDHmO3x4k+zsLqyJHxzv6ikKJWl0eiUF
JUv/mzxiaYsOBiMTYYuueNYegzhzGiW8jzp+j6E3WXTPxwCP2It8/31aBfyuaKcG
B807//VKcHulPONe3emBK7I2KzsJ6UOUs7iHuqrdwoglQKqMC0iyy2/ZFXbu7JJU
cMlHObCNFOGPZxKGsYXG
=5zhn
-----END PGP SIGNATURE-----
Merge tag 'renesas-boards-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards
From Simon Horman:
Renesas ARM based SoC board updates for v3.14
* Global
- Kconfig: Mention Renesas ARM SoCs instead of SH-Mobile
* r7s72100 SoC (RZ/A1H) based Genmai Board
- Add Multiplatform support
- Add Reference DT
* r8a7791 (R-Car M2) based Koelsch board
- Add pinctrl_register_mappings() for Koelsch
- Hook up SW30-SW36 on Koelsch
- Mark GPIO keys as wake-up sources
- Use ->init_late()
- Add Multiplatform support
- Set .debounce_interval for GPIO keys
- Add SW2 to GPIO keys
- Add Led 6, 7 and 8 support
- Add reference DT
- Enable PFC/GPIO
* r8a7790 (R-Car H2) based Lager board
- Add gpio/fixed regulator for SDHI
- Add SPI FLASH support on QSPI
- Mark GPIO keys as wake-up sources
- Use ->init_late()
- Set .debounce_interval for GPIO keys
* r8a7778 (R-Car M1) based Bock-W board
- bockw: remove unused RSND_SSI_CLK_FROM_ADG
- Set .debounce_interval for GPIO keys
- Correct FPGA ioremap area
- Use regulator for MMCIF
* r8a7740 (R-Mobile A1) based Armadillo board
- Correct FSI address size
* sh7374 (SH-Mobile AP4) based Mackerel board
- Use pinconf API to configure pin pull-down
- clk_round_rate() can return a zero to indicate an error
* tag 'renesas-boards-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (75 commits)
ARM: shmobile: lager: add gpio/fixed regulator for SDHI
ARM: shmobile: bockw: remove unused RSND_SSI_CLK_FROM_ADG
ARM: shmobile: armadillo: fixup FSI address size
ARM: Kconfig: Mention Renesas ARM SoCs instead of SH-Mobile
ARM: shmobile: mackerel: Use pinconf API to configure pin pull-down
ARM: shmobile: Lager:add SPI FLASH support on QSPI
ARM: shmobile: mackerel: clk_round_rate() can return a zero to indicate an error
ARM: shmobile: Add pinctrl_register_mappings() for Koelsch
ARM: shmobile: Use ->init_late() on Lager
ARM: shmobile: Hook up SW30-SW36 on Koelsch
ARM: shmobile: koelsch: mark GPIO keys as wake-up sources
ARM: shmobile: Use ->init_late() on Koelsch
ARM: shmobile: lager: mark GPIO keys as wake-up sources
ARM: shmobile: r7s72100 Genmai Multiplatform
ARM: shmobile: r7s72100 Genmai DT reference C bits
ARM: shmobile: r7s72100 Genmai DT reference DTS bits
ARM: shmobile: Initial r8a7791 and Koelsch multiplatform support
ARM: shmobile: koelsch: set .debounce_interval
ARM: shmobile: lager: set .debounce_interval
ARM: shmobile: bockw: add pin pull-up setting for SDHI
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds low level debug uart support to Broadcom mobile based
SOCs.
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Tested-by: Markus Mayer <markus.mayer@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Tested-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There are two SCHED_HRTICK config entries in Kconfig.
This looks like a merge mistake. Fix it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Modern ARM CPUs can perform efficient unaligned memory accesses in
hardware and this feature is relied up on by code such as the dcache
word-at-a-time name hashing.
This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS for these cores and
reworks the kconfig select logic for DCACHE_WORD_ACCESS to use the new
symbol.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With commit 11ec50caed ("word-at-a-time: provide generic big-endian
zero_bytemask implementation"), the asm-generic word-at-a-time code now
provides a zero_bytemask implementation, allowing us to make use of
DCACHE_WORD_ACCESS on big-endian CPUs, providing our
load_unaligned_zeropad function is endianness-clean.
This patch reworks the load_unaligned_zeropad fixup code to work for
both big- and little-endian CPUs, then removes the !CPU_BIG_ENDIAN check
when selecting DCACHE_WORD_ACCESS.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The ASID allocator has to deal with some pretty horrible behaviours by
the CPU, so expand on some of the comments in there so I remember why
we can never allocate ASID zero to a userspace task.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since we only clear entries in the ASID bitmap on a rollover event, the
bitmap tends to consist of a block of consecutive set bits followed by
a block of consecutive clear bits. The exception to this rule is for
ASIDs which have been carried over from a previous generation, but
these are bound by the number of CPUs.
This patch optimises our bitmap searching strategy, so that we search
from the last successful allocation, rather than search from index 1
each time we allocate a new ASID.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With the new ASID allocation algorithm, active ASIDs at the time of a
rollover event will be marked as reserved, so active mm_structs can
continue to operate with the same ASID as before. This in turn means
that we don't need to worry about allocating a new ASID to an mm that
is currently active (installed in TTBR0).
Since updating the pgd and ASID is atomic on LPAE systems (by virtue of
the two being fields in the same hardware register), we can dispose of
the reserved TTBR0 and rely on whatever tables we currently have live.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The definition of virt_addr_valid is that virt_addr_valid should
return true if and only if virt_to_page returns a valid pointer.
The current definition of virt_addr_valid only checks against the
virtual address range. There's no guarantee that just because a
virtual address falls bewteen PAGE_OFFSET and high_memory the
associated physical memory has a valid backing struct page. Follow
the example of other architectures and convert to pfn_valid to
verify that the virtual address is actually valid. The check for
an address between PAGE_OFFSET and high_memory is still necessary
as vmalloc/highmem addresses are not valid with virt_to_page.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When given a compound high page, __flush_dcache_page will only flush
the first page of the compound page repeatedly rather than the entire
set of constituent pages.
This error was introduced by:
0b19f93 ARM: mm: Add support for flushing HugeTLB pages.
This patch corrects the logic such that all constituent pages are now
flushed.
Cc: stable@vger.kernel.org # 3.10+
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The IDE code used to specify the IDE IRQs for chipsets operating in
legacy mode. This appears to no longer work, and this information must
be provided by the arch. Do so. This partially fixes CY82C693 (and
probably others) on Footbridge platforms.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The clockevents code was being told that the footbridge clock event
device ticks at 16x the rate which it actually does. This leads to
timekeeping problems since it allows the clocksource to wrap before
the kernel notices. Fix this by using the correct clock.
Fixes: 4e8d76373c ("ARM: footbridge: convert to clockevents/clocksource")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: <stable@vger.kernel.org>
Cleanup the LEDs code to use ioremap()/writeb() to access the register.
This allows us to move the definitions out of a header file directly
into the ebsa285 support code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Make pgd allocation retry on failure; we really need this to succeed
otherwise fork() can trigger OOMs.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add a one-shot mode for the DC21285 timer. This allows us to use the
NO_HZ modes on this platform.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles to allow non-ARM derivated to be compatible to ARM
cache controller compatibles.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Enable the compiler intrinsic for byte swapping on arch ARM. This
allows the compiler to detect and be able to optimize out byte
swappings, and has a very modest benefit on vmlinux size (Linaro gcc
4.8):
text data bss dec hex filename
2840310 123932 61960 3026202 2e2d1a vmlinux-lart #orig
2840152 123932 61960 3026044 2e2c7c vmlinux-lart #builtin-bswap
6473120 314840 5616016 12403976 bd4508 vmlinux-mxs #orig
6472586 314848 5616016 12403450 bd42fa vmlinux-mxs #builtin-bswap
7419872 318372 379556 8117800 7bde28 vmlinux-imx_v6_v7 #orig
7419170 318364 379556 8117090 7bdb62 vmlinux-imx_v6_v7 #builtin-bswap
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Acked-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
sync_cache_w already includes a dsb, so we can just use sev() directly
then following a cache-sync.
Acked-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
These symbols are only referenced in this source file so can be made
static, and the efficiency table is constant data so can be declared as
such. This avoids polluting the global namespace and fixes warnings
from sparse.
The function arch_scale_freq_power() is still not prototyped or static,
this is a separate issue as this is overriding a weak symbol from the
scheduler which neglects to provide a prototype.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There is a miscompilation of csum_tcpudp_magic() due to the way we pass
the asm() operands in. Fortunately, this doesn't affect the IP code,
but can affect anyone who passes ntohs(udp->len) as the length argument,
or protocols with more than 8 bits.
The problem stems from passing 16-bit operands into an asm() - GCC makes
no guarantees about what may be in the high 16-bits of such a register
passed into assembly which is in the "HI" machine mode.
Address this by changing the way we handle the 16-bit arguments - since
accumulating the protocol and length can never overflow, we can delegate
this to the compiler to perform, and then accumulate it into the
checksum inside the asm(), taking account of the endian-ness via an
appropriate 32-bit rotation.
While we are here, also realise that there's a chance to optimise this
a little: several callers from IP code pass a constant zero as the
initial sum. This is wasteful - if we detect this condition, we can
optimise away one instruction.
Tested-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
