The address of the blsp2_ahb_clk register is incorrect. Fix it.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the
s2mps11 clock driver.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
There is no need for checking if 'clk_table' is not NULL twice (first
after allocation and second at the end of probe()). Also move allocation
of this 'clk_table' to probe from s2mps11_clk_parse_dt as this is
logical place for it.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Add of_clk_del_provider to remove previously registered clock provider.
Add of_node_put to decrement the ref count of clock nodes.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
When it fails to allocate div, gate should be free'd before return
Signed-off-by: Valentin Ilie <valentin.ilie@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Commit 1d9fe6b97 ("clk: divider: Fix best div calculation for power-of-two and
table dividers") introduces a regression in its _table_round_up function.
When the divider passed to this function is greater than the max divider
available in the table, this function returns table's max divider.
Problem is that it causes an infinite loop in clk_divider_bestdiv() because
_next_div() will never return a value greater than maxdiv.
Instead of returning table's max divider, this patch returns INT_MAX.
Reported-by: Fabio Estevam <festevam@gmail.com>
Reported-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
From: Heiko Stuebner <heiko@sntech.de>
Similar to muxes which already have a read-only flag there sometimes
exist dividers which should not be changed by the clock framework
but whose value still should be readable.
Therefore add a READ_ONLY flag similar to the mux-one to clk-divider
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[changed flag bit to BIT(5) as suggested by Tomasz Figa]
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Max Schwarz <max.schwarz@online.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Driver for the R8A7740's clocks that are too specific to be supported by a
generic driver.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
We need "tbclk" clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Initialize the XUSB-related clocks with appropriate parents and rates
for both Tegra114 and Tegra124.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock. It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The parent-to-index mapping for xusb_fs_src is incorrect.
Fix it by adding a mux table.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Enable hardware control of PLLE spread-spectrum, IDDQ, and enable
controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE
will use these controls for power-saving optimizations.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Add clk driver to support clock blocks found on the AXM55xx devices. The driver
provides clock implementations for three different types of clock devices on
the AXM55xx device: PLL clock, a clock divider and a clock mux.
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The MSTP[SC]R registers have clock stop bits, not clock enable bits. The
bit value should thus be inverted in the is_enabled() operation.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch adds of_clk_get_by_clkspec() helper function, which does only
a struct clk lookup from the clock providers. It is used in the subsequent
patch where parsing of a clock from device tree and the lookup from
providers needed to be split.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
- S3C2412, S3C2413, S3C2416 and S3C2443 to use CCF
- S3C2410, S3C2440, S3C2442 to use CCF
- Remove legacy samsung clock from mach-s3c24xx/
- Some of them are missed from previous pull-request
- Clock related sutff got ack from Mike and Tomasz
- Created the last commit due to missing changes
during re-sorting because this branch is provided
as a base to samsung clk tree.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJTeoP9AAoJEA0Cl+kVi2xq+VQP/jKVZmd0FvMeoyoyddUfOxfV
b8jKaVbD/lB7vhPc7XGK9waXBdi6Ajdx71VAAfIfcl+m+xp9XTS0eVirWeP9yh6g
Xbtqp6QhWJfph1iufI/Tmab075lmHI05iprVP3LIJ8fFVpfHbbMLel9SJEDti+sj
+shdWgTdd4Cxl7Y60noo7Y4WEBrC2qpkegC0xut16ZJKdt5WxC4KW2DltC435MB0
b/v7oKLvWr2SvBkDKk7h5aX7z+Ws3ALQ2XfV/CbTkW9LaPFaPqr68V9ZNmHEfeLb
Az7aSlktBAAGTjwDHYOuw5w1eHHrZZBOpJfVKFmPVLGNzqkTAzUWMDQJay/LTRDF
u9fXtJA2cZBuNmuGdAiE8ZxQwbrLFiPC06Ybie+Qq4LiliCzjBfuB+CuSf7bVw2A
jOmU34Cctvyj7JdEZzDDby4baQFgS6NuI5OHnTXjQlfNejtoG0gDSIWWkPm5xr1w
c5ADCyq5UzBCmUzhp4KCyxMnqz9BGMxw96PPLKGAlNNw0i1tp8SUFjzaKyDB6yOm
I60WDNWGC+T4uoNRvkW8sKGQX7thjtR5KVI0cWvgQbBSiycMoMJcKWAmrckGA1In
SPnriO5NpDIOEnV7MQ8pyPLIijhX09xSdDS7wASR9rthC7qnnHmVBjByMQXUi6Th
emxN1xC5mM2kT68u/oWB
=HX4t
-----END PGP SIGNATURE-----
Merge tag 's3c24xx-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
Merge "Samsung S3C24XX updates for 3.16" from Kukjin Kim:
Samsung S3C24XX to use the common clock framework
- S3C2412, S3C2413, S3C2416 and S3C2443 to use CCF
- S3C2410, S3C2440, S3C2442 to use CCF
- Remove legacy samsung clock from mach-s3c24xx/
- Some of them are missed from previous pull-request
- Clock related sutff got ack from Mike and Tomasz
- Created the last commit due to missing changes
during re-sorting because this branch is provided
as a base to samsung clk tree.
* tag 's3c24xx-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (23 commits)
ARM: S3C24XX: fix merge conflict
ARM: S3C24XX: remove SAMSUNG_CLOCK remnants after ccf conversion
ARM: S3C24XX: remove legacy clock code
ARM: S3C24XX: convert s3c2410 to common clock framework
ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock framework
ARM: S3C24XX: add platform code for conversion to the common clock framework
clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442
dt-bindings: add documentation for s3c2410 clock controller
ARM: S3C24XX: enable usage of common dclk if common clock framework is enabled
clk: samsung: add clock driver for external clock outputs
ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when using ccf
ARM: S3C24XX: convert s3c2412 to common clock framework
clk: samsung: add clock controller driver for s3c2412
dt-bindings: add documentation for s3c2412 clock controller
clk: samsung: add plls used by the early s3c24xx cpus
ARM: S3C24XX: only store clock registers when old clock code is active
ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework
ARM: dts: add clock data for s3c2416
ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The IM-PD1 PrimeCells all have pclk assignments though this clock
cannot be controlled, and we need to provide this as a dummy
clock for the PL061 GPIO driver to probe, so let's assign it to
all the cells on the board.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
regressions. As usual most fixes are for platform-specific clock
drivers, but there are also two fixes to the clk core after recent
changes to the way that clock unregistration is handled.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTeQLIAAoJEDqPOy9afJhJcE8QAIZShW4Go9JuA5E2cPb2PiUu
IAm1BTAcbUj0B/sjieDm4q7HP1ZPrgsko4lbf3carAzfs3aWV03yAiILiGg5K4EB
f0ifAARCmWy4iqryKL2KAUkpx+y8laxa6NMrby1IpVYqOluEI4AznehlAJDuhvI4
6rBqLP1R3BjPduqXdnB/vWLLFRKK2TiWnuQu1qeBWz27NMm0bhvKEkmKwpyeklyb
fnK+ImGn4TojQG12RfwnpDZUaYWba+HD50kBLi8aumlgdYscY+mVJnNXtya1V6hi
datzqIJmnO32nYOiBlZezPY1L2yU/IaNN0Cn/tEyRSt74peDLLP6jsA+VzGXmHxo
K93aLy/pWVkQsDhC2xSVL3FeevhG+2fSrcLdLAMj24ydFYMAXnviYch/opBeCFm4
t3hJUtD1MfPHPAFCPFgkJoMWeQPEHOUTAJ80Sc1HN02RUTa61i2JBt19Qo46FYdM
82QpHOReXVZOqJT1g11topv7ql3MFYUiesofmH3SCL35ufjkgI9yHkYRoJD6VSh9
UwkMPLHfezmOs7Afy2q3XAxYjcdQSir4BZj6k4WqTWPJEqgKe75gLFJ9CbCCxVWx
wy0hjsJ5tJX1arB0LT37CV8wY2GoHn73j2x+H+PXt8CT8sfJsGb6gVudyIqEqV66
iZKcyhBUVjKeeBtrinq+
=JwFU
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework fixes from Mike Turquette:
"Clock framework and driver fixes, all of which fix user-visible
regressions.
As usual most fixes are for platform-specific clock drivers, but there
are also two fixes to the clk core after recent changes to the way
that clock unregistration is handled"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk: tegra: Fix wrong value written to PLLE_AUX
clk: shmobile: clk-mstp: change to using clock-indices
clk: Fix slab corruption in clk_unregister()
clk: Fix double free due to devm_clk_register()
clk: socfpga: fix clock driver for 3.15
clk: divider: Fix best div calculation for power-of-two and table dividers
clk: bcm281xx: don't use unnamed structs or unions
With common OF_DECLARE macros, a semi-colon will be required for
CLK_OF_DECLARE. Add the missing semi-colon to ti,gate-clock.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Adding function type checking to CLK_OF_DECLARE found a type mismatch with
sunxi_init_clocks. The function takes a single struct device_node
parameter.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Use for_each_matching_node_and_match instead of for_each_matching_node plus
of_match_node to avoid searching the DT twice for each node.
The sunxi DT scanning code should really be re-worked rather than have
its own private matching infrastructure. It is working around needing a
function pointer and a data pointer for each compatible match.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: "Emilio López" <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Adding function type checking to CLK_OF_DECLARE found a type mismatch with
rk2928_gate_clk_init. The function only takes a single struct device_node
parameter.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Fractional divider clocks are fairly common. This adds basic
type for them.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Exynos5800 clock structure is mostly similar to 5420 with only
a small delta changes. So the 5420 clock file is re-used for
5800 also. The common clocks for both are seggreagated and few
clocks which are different for both are separately initialized.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
When consolidating the msm8660 GCC probe code I forgot to keep
around these temporary clock registrations. Put them back so the
clock tree is not entirely orphaned.
Fixes: 49fc825f0c (clk: qcom: Consolidate common probe code)
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The value written to PLLE_AUX was incorrect due to a wrong variable
being used. Without this fix SATA does not work.
Cc: stable@vger.kernel.org
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: improved changelog]
Move the Kconfig entry for Versatile (& Express) clock drivers
into a separate file and add individual options for sp810
and vexpress_osc drivers, as they are optional in some
configurations and may have separate dependencies.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
The impd1 code on mach-integrator can be a loadable module,
so we have to export icst_clk_register, integrator_impd1_clk_init
and integrator_impd1_clk_exit.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
__clk_get_hw is supposed to be used by clk providers, not clk consumers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
and function clocks for individual IPs.
The CMU of Exynos3250 includes following clock doamins:
- CPU block for Cortex-A7 MPCore processor
- LEFTBUS/RIGHTBUS block
- TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Karol Wrona <k.wrona@samsung.com>
Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
This patch replaces PLAT_SAMSUNG with COMMON_CLK_SAMSUNG for Samsung
common clock support. Any Samsung SoC want to use Samsung common clock
infrastructure can simply select COMMON_CLK_SAMSUNG.
CC: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch moves S3C24XX specific clock Kconfig options into
"clk/samsung/Kconfig" and also removes COMMON_CLK selection from
"mach-s3c24xx/Kconfig" as S3C24XX_COMMON_CLK is selecting it's dependency.
CC: Ben Dooks <ben-linux@fluff.org>
CC: Kukjin Kim <kgene.kim@samsung.com>
CC: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds new Kconfig file for adding new COMMON_CLK_SAMSUNG option.
Samsung platforms can select this for using common clock infrastructure.
CC: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds more register offsets to the list for
preserving their values during S2R.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds some missing miscellaneous clocks specific
to exynos5420.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds the missing MAU block specific clocks.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch corrects the wrong parent-child relationship
between sysmmu-mfc clocks.
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds more clocks from FSYS and FSYS2 blocks
and uses GATE_IP_* registers for gating IPs.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch fixes some parent-child relationships according
to the latest datasheet and adds more clocks related to
PERIS and GEN blocks.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
