Unconditionally register the PCI-E bus, even if the link is currently
down. When the link is brought up the bus can be scanned through
/sys/bus/pci/rescan or otherwise. Since the HW has no interrupt for
link up, userspace will have to take care of the timing.
An earlier version of this was contingent on CONFIG_HOTPLUG, but
that is being removed from the kernel.
This also fixes printing the link up/down message to be displayed
on one line (structured logging broke this?)
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
- add missing gpio interrupt lines to dove dt
- fix bad logic for printing MPP error message on orion boards
- build proper serial port driver after changing mvebu DT compatible property
- This is a change to mvebu_defconfig that I wouldn't usually push out as a
fix. However, the commit
b24212f arm: mvebu: Use dw-apb-uart instead of ns16650 as UART driver
changed the serial driver for the board in the dts file. without the patch
I've included in this pull, users won't see any log messages.
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Merge tag 'tags/mvebu_fixes_for_v3.8-rc6' into mvebu/drivers
fixes for v3.8-rc6
- add missing gpio interrupt lines to dove dt
- fix bad logic for printing MPP error message on orion boards
- build proper serial port driver after changing mvebu DT compatible property
- This is a change to mvebu_defconfig that I wouldn't usually push out as a
fix. However, the commit
b24212f arm: mvebu: Use dw-apb-uart instead of ns16650 as UART driver
changed the serial driver for the board in the dts file. without the patch
I've included in this pull, users won't see any log messages.
This adds a subdriver for the AB8500 pinctrl portions.
As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.
Acked-by: Olof Johansson <olof@lixom.net>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the AB8500 core driver, which will be utilized by
the follow-on drivers for different ABx500 variants.
Sselect the driver from the DBX500_SOC, as this chip is
powering and clocking that SoC.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin controller is an inherent part of the SoC, without
it the system will not boot, thus it needs to be selected
from Kconfig.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The preference is to use '-' instead of '_' in compatible strings.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Move sp810 header to a more generic location,
mainly to share it with arm64
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Merge tag 'vexpress/drivers-for-3.9' of git://git.linaro.org/people/pawelmoll/linux into next/drivers
From Pawel Moll:
Versatile Express related driver updates for 3.9:
* Move sp810 header to a more generic location,
mainly to share it with arm64
* tag 'vexpress/drivers-for-3.9' of git://git.linaro.org/people/pawelmoll/linux:
arm: Move sp810.h to include/linux/amba/
+ Linux 3.8-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
From Nicolas Ferre:
Two little Device Tree fixes for USART on at91sam9x5.
* tag 'at91-fixes' of git://github.com/at91linux/linux-at91:
ARM: at91/at91sam9x5.dtsi: fix usart3 TXD
ARM: at91: at91sam9x5: fix usart3 pinctrl name
Since it is now used by code under drivers/clk/ it makes sense for this
file to be in a more generic location. This is required for building
vexpress support on arm64.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Add WAIT mode (ARM core clock gating) support to imx6q cpuidle driver.
As WAIT mode is broken on imx6q TO 1.0 and 1.1, it only enables the
support for revision 1.2 with chicken bit set.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Move imx6q_cpuidle_driver into a separate file as more codes will
be added when WAIT mode gets implemented as cpuidle.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The return of v2_set_next_event() will lead to an infinite loop in
tick_handle_oneshot_broadcast() - "goto again;" with imx6q WAIT mode
(to be enabled). This happens because when global event did not expire
any CPU local events, the broadcast device will be rearmed to a CPU
local next_event, which could be far away from now and result in a
max_delta_tick programming in set_next_event().
Fix the problem by detecting those next events with increments larger
than 0x7fffffff, and simply return zero in that case.
It leaves mx1_2_set_next_event() unchanged since only v2_set_next_event()
will be running with imx6q WAIT mode support.
Thanks Russell King for helping understand the problem.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Comment for usart3 TXD (TXD3) is correct, dt code is wrong.
Signed-off-by: Douglas Gilbert <dgilbert@interlog.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The renaming of pinctrl_uart3 to pinctrl_usart3 was missed in
commit 9e3129e (ARM: at91: fix usart/uart namimg in pinctrl).
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Previously clock rates were set after initialization of timer.
Therefore the timer used the default extal1 clock rate (25MHz)
instead of the correct rate for this board (24MHz).
Signed-off-by: Hideki EIRAKU <hdk@igel.co.jp>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
sh73a0 deals fine with disabling any core, so we should permit it.
Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Method to disable any core to be used on platforms where CPU0 does not
need special treatment.
Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- First an ACKed MFD patch deleting the only consumer
of these cpu_is* functions outside of mach-ux500
- Introduce a new local cpu_is_u8580() in this patch
set to avoid clashing with other patch sets.
- Finally de-globalize <mach/id.h>.
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Merge tag 'ux500-no-idh' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/cleanup
From Linus Walleij:
Removal of the <mach/id.h> include from ux500
- First an ACKed MFD patch deleting the only consumer
of these cpu_is* functions outside of mach-ux500
- Introduce a new local cpu_is_u8580() in this patch
set to avoid clashing with other patch sets.
- Finally de-globalize <mach/id.h>.
* tag 'ux500-no-idh' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: de-globalize <mach/id.h>
ARM: ux500: Introduce cpu_is_u8580()
mfd: prcmu: delete pin control helpers
Signed-off-by: Olof Johansson <olof@lixom.net>
* Correct interrupt definitions for WDT node in
V2P-CA15 and V2P-CA15_A7 Device Trees
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Merge tag 'vexpress/fixes-for-3.9' of git://git.linaro.org/people/pawelmoll/linux into next/fixes-non-critical
From Pawel Moll:
Versatile Express related fixes for 3.9
* Correct interrupt definitions for WDT node in
V2P-CA15 and V2P-CA15_A7 Device Trees
* tag 'vexpress/fixes-for-3.9' of git://git.linaro.org/people/pawelmoll/linux:
ARM: vexpress: Fix wdt interrupt in ca15{-tc1,_a7} dts
Signed-off-by: Olof Johansson <olof@lixom.net>
- remove unneeded #includes for mach-dove
- remove unneeded #includes and code for the nsa310
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Merge tag 'cleanup_for_v3.9_round2' of git://git.infradead.org/users/jcooper/linux into next/cleanup
From Jason Cooper:
cleanup for v3.9 round2
- remove unneeded #includes for mach-dove
- remove unneeded #includes and code for the nsa310
* tag 'cleanup_for_v3.9_round2' of git://git.infradead.org/users/jcooper/linux:
ARM: dove: cleanup includes
ARM: kirkwood: nsa310: cleanup includes and unneeded code
Fix some whitespace problems introduced by commit
da03ce65b5 ("OMAP3: powerdomain data:
add voltage domains"). Also, improve the documentation for the struct
powerdomain.flags field.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
The atomic usecounts seem to be confusing, and are no longer needed
since the operations that they are attached to really should take
place under lock. Replace the atomic counters with simple integers,
protected by the enclosing powerdomain spinlock.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Split the clkdm_(add|del)_(wk|sleep)dep() functions into lockless and
locking versions -- this will be needed in a subsequent patch. Also,
while here, remove the leading underscore, since these are not
currently static functions. And for functions that have
kerneldoc-style comment blocks, but which are missing the initial
'/**' tag, fix the tag to indicate that they are kerneldoc.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
There's no need to preserve the autodep handling code in
mach-omap2/cm2xxx.c, since no autodeps are defined for these chips.
Hopefully they'll never be needed, but if in some future case they are,
this code can be added back in.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add a per-powerdomain spinlock. Use that instead of the clockdomain
spinlock. Add pwrdm_lock()/pwrdm_unlock() functions to allow other
code to acquire or release the powerdomain spinlock without reaching
directly into the struct powerdomain.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jean Pihet <jean.pihet@newoldbits.com>
Move omap_set_pwrdm_state() from the PM code to the powerdomain code,
and refactor it to split it up into several functions. A subsequent patch
will rename it to conform with the existing powerdomain function names.
This version includes some additional documentation, based on a
suggestion from Jean Pihet. It also modifies omap_set_pwrdm_state()
to not bail out early unless both the powerdomain current power state
and the next power state are equal. (Previously it would terminate
early if the next power state was equal to the target power state,
which was insufficiently rigorous.)
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jean Pihet <jean.pihet@newoldbits.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tero Kristo <t-kristo@ti.com>
Drop an unnecessary pwrdm_wait_transition() from mach-omap2/pm.c -
it's called by the subsequent pwrdm_state_switch().
Also get rid of pwrdm_wait_transition() in the powerdomain code - there's
no longer any need to export this function.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Don't attempt to put clockdomains to sleep; this should be handled by the
clock framework. It should be enough to program the next-power-state,
and then let the code in omap_pm_clkdms_setup() deal with the rest.
Start out by programming the MPU and CORE powerdomains to stay ON.
Then control the MPU and CORE powerdomain states directly in
omap2_enter_full_retention() and omap2_enter_mpu_retention(). Not the
most optimal way to do it, but certainly is the most conservative until
OMAP2xxx PM is working again.
Get rid of the open-coded PM_PWSTCTRL_MPU writes in
omap2_enter_mpu_retention(); use the powerdomain code instead.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
In clkdm_sleep(), the powerdomain should be eligible to switch power
states right after the call to the low-level clockdomain sleep
function. We should have been tracking that with the
pwrdm_state_switch() code, but we weren't, for whatever reason. Fix that.
This resolves the "pwrdm state mismatch(cam_pwrdm) 3 != 0" that appears
during the OMAP4460 Pandaboard-ES PM test, e.g. here:
http://www.pwsan.com/omap/testlogs/test_v3.8-rc5/20130126003323/pm/4460pandaes/4460pandaes_log.txt
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Fix the trace in the case a power domain did not hit the desired
state, as reported by Paul Walmsley.
Reported-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Jean Pihet <j-pihet@ti.com>
[paul@pwsan.com: split this fix off from the patch
"ARM: OMAP2+: PM debug: trace the functional power domains states"]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Avoid programming the MPU and CORE powerdomain next-power-state
registers if those powerdomains will never enter low-power states
(e.g., the state that people refer to as "C1").
To avoid making assumptions about CPUIdle states based on their order
in the list, use a flag to mark CPUIdle states that don't enter
powerdomain low-power states.
Avoid a previous-power-state register read on the MPU powerdomain
unless we know that the MPU was supposed to go OFF during the last
state transition. Previous-power-state register reads can be very
expensive, so it's worth avoiding these when possible.
Since the CORE_L3 clockdomain can't go inactive unless the MPU is active,
there's little point blocking autoidle on the CORE_L3 clockdomain in "C1"
state, since we've programmed the MPU clockdomain to stay active.
Remove the unnecessary code.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
This patch cleans unneccessary includes and reorders the remaining
includes in common dove code.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
After removing the unneeded linux/i2c.h, linux/of.h was needed for
of_machine_is_compatible(). i2c.h had included of.h.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The patch: "ARM: use common irqchip_init for GIC init"
(sha1: 0529e315bb)
should also add linux/irqchip.h header.
Error message:
arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init'
undeclared here (not in a function)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
- add missing gpio interrupt lines to dove dt
- fix bad logic for printing MPP error message on orion boards
- build proper serial port driver after changing mvebu DT compatible property
- This is a change to mvebu_defconfig that I wouldn't usually push out as a
fix. However, the commit
b24212f arm: mvebu: Use dw-apb-uart instead of ns16650 as UART driver
changed the serial driver for the board in the dts file. without the patch
I've included in this pull, users won't see any log messages.
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Merge tag 'mvebu_fixes_for_v3.8-rc6' of git://git.infradead.org/users/jcooper/linux into fixes
From Jason Cooper:
fixes for v3.8-rc6
- add missing gpio interrupt lines to dove dt
- fix bad logic for printing MPP error message on orion boards
- build proper serial port driver after changing mvebu DT compatible property
- This is a change to mvebu_defconfig that I wouldn't usually push out as a
fix. However, the commit
b24212f arm: mvebu: Use dw-apb-uart instead of ns16650 as UART driver
changed the serial driver for the board in the dts file. without the patch
I've included in this pull, users won't see any log messages.
* tag 'mvebu_fixes_for_v3.8-rc6' of git://git.infradead.org/users/jcooper/linux:
arm: mvebu: i2c come back in defconfig
arm: plat-orion: fix printing of "MPP config unavailable on this hardware"
Dove: activate GPIO interrupts in DT
The irqs available on the machine and even the bit settings in the
irq registers differ a lot through all the s3c24xx subarchitectures.
This results in each subarch having its own irq init which adds its
specific irqs to the base ones created in plat-s3c24xx/irq.c.
This of course makes a future move to devicetree hard to implement.
Therefore this patch transforms the base irq handling to a declarative
style, where the irq types as well as its parent/child relationship
gets read from a predefined datastructure, which later on can hopefully
be easily represented in devicetree too.
It should also be easy to include the subarch specific irqs here
in later patches, reducing code size and duplication.
It should not affect anything outside of the file, as the original
irq numbers and their handling are preserved (hopefully) correctly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
From Kukjin Kim:
This fixes compatible values for exynos pinctrl and crash on soft reset,
tick and alarm irq numbers on exynos5440 and uninitialized variable on
s3c24xx.
* 'v3.8-samsung-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Fix crash on soft reset on EXYNOS5440
ARM: dts: fix tick and alarm irq numbers for exynos5440
ARM: dts: fix compatible value for exynos pinctrl
ARM: dts: Fix compatible value of pinctrl module on EXYNOS5440
ARM: S3C24XX: fix uninitialized variable warning
Signed-off-by: Olof Johansson <olof@lixom.net>
As the wdt nodes have the gic as their interrupt-parent, their
interrupts property should be 3 cells in format described in the gic
devicetree binding document.
This patch fixes the interrupts property in the wdt nodes to be in the
correct format.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Tegra114 has the GPIO controllers with 8 GPIO bank and each bank
supports 32 pins.
Add DT entry for GPIO controller. Tegra114 GPIO controller is
compatible with Tegra30 GPIO controller driver.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Select PINCTRL and PINCTRL_TEGRA114 for enabling Tegra114 pincontrol
driver for Tegra114 SoC.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use functional name for DT entry instead of h/w name.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use functional name for DT entry instead of h/w name.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The SDHCI and I2C subsytems and drivers are enabled.
Various filesystems are enabled for use with the SDHCI driver.
Various other options expected by distros are enabled. This allows the
"Raspbian" filesystem published by the Raspberry Pi Foundation to boot
to a serial console prompt.
This branch is based on v3.8-rc3.
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Merge tag 'bcm2835-for-3.9-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/boards
From Stephen Warren:
ARM: bcm2835: defconfig update
The SDHCI and I2C subsytems and drivers are enabled.
Various filesystems are enabled for use with the SDHCI driver.
Various other options expected by distros are enabled. This allows the
"Raspbian" filesystem published by the Raspberry Pi Foundation to boot
to a serial console prompt.
This branch is based on v3.8-rc3.
* tag 'bcm2835-for-3.9-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: defconfig updates
Signed-off-by: Olof Johansson <olof@lixom.net>
The SoC's SDHCI and MMC controllers are added to device tree, and enabled
in the Raspberry Pi board device tree. Some fixed clocks are added to the
device tree to support these drivers. These could be replaced by real
clocks in the future.
A hard-coded memreserve is removed from device tree; the bootloader should
specify the correct memory node content instead, since the memory layout
is dynamic.
This branch is based on v3.8-rc3.
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Merge tag 'bcm2835-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/dt
From Stephen Warren:
ARM: bcm2835: device tree updates
The SoC's SDHCI and MMC controllers are added to device tree, and enabled
in the Raspberry Pi board device tree. Some fixed clocks are added to the
device tree to support these drivers. These could be replaced by real
clocks in the future.
A hard-coded memreserve is removed from device tree; the bootloader should
specify the correct memory node content instead, since the memory layout
is dynamic.
This branch is based on v3.8-rc3.
* tag 'bcm2835-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: fix clock node aliasing in device tree
ARM: bcm2835: add I2C controllers to DT
ARM: bcm2835: add SDHCI node to DT
ARM: bcm2835 rpi: remove hard-coded memreserve from DT
Signed-off-by: Olof Johansson <olof@lixom.net>
