PIT clock events work already and the PIT handling is the same for
i386 and x86_64. x86_64 does not support PIT as a clock source, so
disable the PIT clocksource for x86_64.
Prepare i8253.h to be shared with x8664
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Add the x8664 specific bits (mapping) to share the hpet code later.
Move the reserve_platform_timer call to late init. This is necessary
for x86_64, as hpet enable() is called before memory is setup. i386
calls it in late_time_init, but it does not hurt to do it later for
both.
Pull in the x8664 hpet disable command line option as well.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
The hpet implementations of i386 and x8664 has been mostly the same
before the clock events conversion of i386. The clock events
conversion of i386 hpet is already done. So it makes sense to share
the code for the x86_64 clock events conversion.
Abstract out the mapping functions.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Move the TSC calibration code to tsc.c. Reimplement it so the
pm timer can be used as a reference as well.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
TSC must be verified by a continous and reliable clocksource to
allow high resolution timers and or dynamic ticks.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Add support for an MFGPT clock event device; this allows us to use MFGPTs as
the basis for high-resolution timers.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Andres Salomon <dilinger@debian.org>
Cc: Andi Kleen <ak@suse.de>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: john stultz <johnstul@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This adds support for Multi-Function General Purpose Timers. It detects the
available timers during southbridge init, and provides an API for allocating
and setting the timers. They're higher resolution than the standard PIT, so
the MFGPTs come in handy for quite a few things.
Note that we never clobber the timers that the BIOS might have opted to use;
we just check for unused timers.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Andres Salomon <dilinger@debian.org>
Cc: Andi Kleen <ak@suse.de>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Disable irq balancing on IRQ0. Several SIS chipsets lock up when you try to
change affinity of IRQ #0.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Cc: john stultz <johnstul@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
The clock events merge introduced a change to the nmi watchdog code to
handle the not longer increasing local apic timer count in the
broadcast mode. This is fine for UP, but on SMP it pampers over a
stuck CPU which is not handling the broadcast interrupt due to the
unconditional sum up of local apic timer count and irq0 count.
To cover all cases we need to keep track on which CPU irq0 is
handled. In theory this is CPU#0 due to the explicit disabling of irq
balancing for irq0, but there are systems which ignore this on the
hardware level. The per cpu irq0 accounting allows us to remove the
irq0 to CPU0 binding as well.
Add a per cpu counter for irq0 and evaluate this instead of the global
irq0 count in the nmi watchdog code.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
The next_event member of the clock event device is used to keep track
of the next periodic event. For one shot only devices it is wrong to
clear the variable, as the next event will be based on it.
Pointed out by Ralf Baechle
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Migration aid to allow preparatory patches which introduce not yet
used parts of clock events code.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
We register a simple trigger so make sure we use the corresponding
unregister function.
(Also means we get a dummy function when triggers aren't compiled in)
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
a function pxa_init_irq_set_wake() was introduced, so that
processor specific code could install their own version
code setting PFER and PRER registers within pxa_gpio_irq_type
are removed, and the edge configuration is postponed to the
(*set_wake) and copies the GRER and GFER register, which will
always be set up correctly by pxa_gpio_irq_type()
Signed-off-by: eric miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This definition produces processor specific code in generic function
pxa_gpio_mode(), thus creating inconsistencies for support of pxa25x
and pxa27x in a single zImage.
As David Brownell suggests, make it a run-time variable and initialize
at run-time according to the number of GPIOs on the processor. For now
the initialization happens in pxa_init_irq_gpio(), since there is
already a parameter for that, besides, this is and MUST be earlier
than any subsequent calls to pxa_gpio_mode().
Signed-off-by: eric miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
since both u-boot and blob support passing MACH_TYPE_LUBBOCK to the
kernel, it should be quite safe to remove this
Signed-off-by: eric miao <eric.y.miao@gmail.com>
Acked-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Extracted from patch by Eric Miao, this adds the cpu_is_xxx() macros
for identifying PXA3 SoCs.
Signed-off-by: eric miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Allow the generic clock support code to fiddle with the CKEN register
and mark pxa_set_cken() deprecated.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
get_lcdclk_frequency_10khz() is now redundant, remove it. Hide
pxa27x_get_lcdclk_frequency_10khz() from public view.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rename pxa25x and pxa27x memory/lcd/core clock functions, and
select the correct version at run time.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than using the compile-time constant CLOCK_TICK_RATE, select
the clock tick rate at run time. We organise the selection so that
PXA3 automatically falls out with the right tick rate.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The previous implementation was relying on compile time optimizations
based on a constant clock rate. However, support for different PXA
flavors in the same kernel binary requires that the clock be selected at
run time, so here it is.
Let's move this code to a more appropriate location while at it.
Signed-off-by: Nicolas Pitre <npitre@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
drivers/scsi/gdth.c: In function ‘gdth_search_dev’:
drivers/scsi/gdth.c:646: warning: ‘pci_find_device’ is deprecated
(declared at include/linux/pci.h:482)
drivers/scsi/gdth.c: In function ‘gdth_init_isa’:
drivers/scsi/gdth.c:857: error: ‘gdth_irq_tab’ undeclared (first use in
this function)
drivers/scsi/gdth.c:857: error: (Each undeclared identifier is reported
only once
drivers/scsi/gdth.c:857: error: for each function it appears in.)
drivers/scsi/gdth.c: In function ‘gdth_copy_internal_data’:
drivers/scsi/gdth.c:2362: warning: unused variable ‘sg’
Looking into the code I notice that gdth_irq_tab is not declared with
CONFIG_ISA=y and !CONFIG_EISA.
The values seem to be same in 2.6.23 (I am not sure why it has been put
with #ifdefs in -mm) so I have just modified the #ifdef to take care of
CONFIG_ISA as well.
Signed-off-by: Dhaval Giani <dhaval@linux.vnet.ibm.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Since scsi_esp_{,un}register() are EXPORT_SYMBOL'ed, these functions
(and the functions they use) can't be __dev{init,exit}.
Based on a bug report by Rob Landley.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
gdth_execute() will issue an internal, none scsi-standard commands
onto __gdth_queuecommand(). Since it is not recommended to set
struct scsi_cmnd IO members in llds, gdth now uses internal IO
members for IO. In the case of gdth_execute() these members will be
set properly. In case the command was issued from scsi-ml
(by gdth_queuecommand) they will be set from scsi IO accessors.
* define gdth IO accessors and use them throughout the driver.
* use an sg-of-one in gdth_execute() and fix gdth_special_cmd()
accordingly.
* Clean the not use_sg code path and company
Signed-off-by Boaz Harrosh <bharrosh@panasas.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
- Cleanup the rest of the scsi_cmnd->SCp members and move them
to gdth_cmndinfo:
SCp.this_residual => priority
SCp.buffers_residual => timeout
SCp.Status => status and dma_dir
SCp.Message => info
SCp.have_data_in => volatile wait_for_completion
SCp.sent_command => OpCode
SCp.phase => phase
- Two more members will be naturally removed in the !use_sg cleanup
TODO: What is the meaning of gdth_cmndinfo.phase? (rhetorically)
Signed-off-by Boaz Harrosh <bharrosh@panasas.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
- scsi_cmnd and specifically ->SCp of, where heavily abused
with internal meaning members and flags. So introduce a new
struct gdth_cmndinfo, put it on ->host_scribble and define a
gdth_cmnd_priv() accessor to retrieve it from a scsi_cmnd.
- The structure now holds two members:
internal_command - replaces the IS_GDTH_INTERNAL_CMD() croft.
sense_paddr - which was a 64-bit spanning on 2 32-bit members of SCp.
More overloaded members from SCp and scsi_cmnd will be moved in a later
patch (For easy review).
- Split up gdth_queuecommand to an additional internal_function. The later
is the one called by gdth_execute(). This will be more evident later in
the scsi accessors patch, but it also facilitates in the differentiation
between internal_command and external. And the setup of gdth_cmndinfo of
each command.
Signed-off-by Boaz Harrosh <bharrosh@panasas.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
- Places like Initialization and Reset that Just loop on all devices can
use the link list with the list_for_each_entry macro.
But the io_ctrl from user mode now suffers performance-wise because
code has to do a sequential search for the requested host number.
I have isolated this search in a gdth_find_ha(int hanum) member
for future enhancement if needed.
Signed-off-by Boaz Harrosh <bharrosh@panasas.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
- Use scsi_add_host and friends and track instances ourselves. And
generally modernize the driver's structure.
- TODO: Next we can remove the controller table
- TODO: Fix use of deprecated pci_find_device()
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Boaz Harrosh <bharrosh@panasas.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
- gdth_get_status() returns a single device interrupt IStatus
- gdth_interrupt split to __gdth_interrupt() that receives
flags if is called from gdth_wait().
- Use dev_id passed from kernel and do not loop on all
controllers.
- gdth_wait(), get read of all global variables and call the new
__gdth_interrupt with these variables on the stack
Signed-off-by Boaz Harrosh <bharrosh@panasas.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
* remove pointless pci_dev_to_dev() wrapper. Just directly reference
the embedded struct device like everyone else does.
* pata_cs5520: delete cs5520_remove_one(), it was a duplicate of
ata_pci_remove_one()
* linux/libata.h: don't bother including linux/pci.h, we don't need it.
Simply declare 'struct pci_dev' and assume interested parties will
include the header, as they should be doing anyway.
* linux/libata.h: consolidate all CONFIG_PCI declarations into a
single location in the header.
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
PMP registers used to be accessed with dedicated accessors ->pmp_read
and ->pmp_write. During reset, those callbacks are called with the
port frozen so they should be able to run without depending on
interrupt delivery. To achieve this, they were implemented polling.
However, as resetting the host port makes the PMP to isolate fan-out
ports until SError.X is cleared, resetting fan-out ports while port is
frozen doesn't buy much additional safety.
This patch updates libata PMP support such that PMP registers are
accessed using regular ata_exec_internal() mechanism and kills
->pmp_read/write() callbacks. The following changes are made.
* PMP access helpers - sata_pmp_read_init_tf(), sata_pmp_read_val(),
sata_pmp_write_init_tf() are folded into sata_pmp_read/write() which
are now standalone PMP register access functions.
* sata_pmp_read/write() returns err_mask instead of rc. This is
consistent with other functions which issue internal commands and
allows more detailed error reporting.
* ahci interrupt handler is modified to ignore BAD_PMP and
spurious/illegal completion IRQs while reset is in progress. These
conditions are expected during reset.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Implement ATA_PFLAG_RESETTING. This flag is set while reset is in
progress. It's set before prereset is called and cleared after reset
fails or postreset is finished.
This flag itself doesn't have any function. It will be used by LLDs
to tell whether reset is in progress if it needs to behave differently
during reset.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Add @timeout argument to ata_exec_internal[_sg](). If 0, default
timeout ata_probe_timeout is used.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Asynchronous notification on ICH9 didn't work because it didn't write
AN FIS into the RX area - it only updates SNotification. Also,
snooping SDB_FIS RX area is racy against further SDB FIS receptions.
Let sata_async_notification() determine using SNTF if it's available
and snoop RX area iff SNTF isn't available
Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Now that we have pp->intr_mask, move PORT_IRQ_BAD_PMP enabling to
ahci_pmp_attach/detach() where it belongs.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
- Based on same patch from Christoph Hellwig <hch@lst.de>
- Get rid of all the indirection in the Scsi_Host private data and always
put the gdth_ha_str directly into it.
- Change all internal functions prototype to recieve an "gdth_ha_str *ha"
pointer directlly and kill all that redundent access to the "gdth_ctr_tab[]"
controller-table.
Signed-off-by: Boaz Harrosh <bharrosh@panasas.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
ahci had problems with NCQ over PMP and NCQ used to be disabled while
PMP was attached. After fixing the problem, the temporary NCQ
disabling code wasn't removed completely. Kill the remaining piece.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
