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171 commits

Author SHA1 Message Date
Andrew Isaacson
93ce2f524e Add support for SB1A CPU. 
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:46 +01:00
Andrew Isaacson
d121ced21d Sibyte fixes 
Fix typo in cpu_probe_sibyte.
    
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:45 +01:00
Ralf Baechle
8afcb5d829 Detect 4KSD and treat it like 4KSc. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:36 +01:00
Ralf Baechle
02cf211968 Cleanup the mess in cpu_cache_init. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:32 +01:00
Thiemo Seufer
075e7502d9 R4600 has 32 FPRs. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:58 +01:00
Pete Popov
bdf21b18b4 Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:54 +01:00
Ralf Baechle
8f40611d2b Detect the MIPS R2 vectored interrupt, external interrupt controller 
options and the precense of the MT ASE.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:51 +01:00
Ralf Baechle
55d04dff0f New kernel option nowait allows disabling the use of the wait instruction. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:48 +01:00
Ralf Baechle
bbc7f22f6d Detect the 34K. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:45 +01:00
Maciej W. Rozycki
d5b6f1db5d For MIPS32/MIPS64 cp0.config.mt == 1 implies a standard (R4k-style) 
TLB, so no need to set it separately for each implementation.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:19 +01:00
Ralf Baechle
e50c0a8fa6 Support the MIPS32 / MIPS64 DSP ASE. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:17 +01:00
Ralf Baechle
10f650db1b 64-bit fixes for Alchemy code ;) 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:17 +01:00
Ralf Baechle
b382fe8483 No point in checking cpu_has_tlb before we've computed the CPU options. 
So for now we just unconditionally set the option - Linux wouldn't
work without a TLB anyway.
    
Setting MIPS_CPU_4KTLB was missing for Alchemy and Sandcraft, add that
back.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:13 +01:00
Ralf Baechle
4194318c39 Cleanup decoding of MIPSxx config registers. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:12 +01:00
Ralf Baechle
f03da6e28e Fix BogoMIPS display on UP and some minor cosmetical things. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:05 +01:00
Ralf Baechle
2b07bd0235 Detect the 4KEcR2 and for now detect handle it like the 4KEc. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:03 +01:00
Pete Popov
fe359bf584 Fixed buglet with previous patch that broke non au1x builds. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:02 +01:00
Pete Popov
494900af68 Remove CONFIG_PM dependency from au1x wait in cpu_probe. 
Additional work necessary to completely remove that config option.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:02 +01:00
Pete Popov
e3ad1c23ba Base Au1200 2.6 support. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:47 +01:00
Adrian Bunk
ab1418a316 [PATCH] more vr4181 removal 
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Cc: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
 2005-09-05 00:06:03 -07:00
Linus Torvalds
1da177e4c3 Linux-2.6.12-rc2 
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
 2005-04-16 15:20:36 -07:00