Simplify the procedure by checking if there is any DIMM in each channel.
This patch will fix the bugs such as when there is no DIMMs under
certain node, two DIMMs in the same channel, and only one DIMM in each
channel of the node.
Borislav: minor fixups
Signed-off-by: Wan Wei <wanwei@mail.dawning.com.cn>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Simplify code flow and make sure return value is always valid since
further driver init depends on it. Carve out long warning string and
make code more readable. Shorten some names, while at it.
There should be no functional change resulting from this patch.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Peter noticed that we have 3 ways of referring to the idle thread:
[idle]:0
swapper:0
swapper-0
Standardize on 'swapper:0'.
Reported-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Use 'perf sched latency' to track the current task based on
context-switch events, and flag the cases where there's some
impossible transition: such as a PID being switched out that
was not switched in.
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Output such lost event and state machine weirdness stats:
TOTAL: | 14974.910 ms | 46384 |
---------------------------------------------------
INFO: 8.865% lost events (19132 out of 215819, in 8 chunks)
INFO: 0.198% state machine bugs (49 out of 24708) (due to lost events?)
And increase buffering to -m 1024 (4 MB) by default. Since we
use output multiplexing that kind of space is needed.
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
-tip testing found the following build failure (config attached):
drivers/built-in.o: In function `amd64_check':
amd64_edac.c:(.text+0x3e9491): undefined reference to `amd_decode_nb_mce'
drivers/built-in.o: In function `amd64_init_2nd_stage':
amd64_edac.c:(.text+0x3e9b46): undefined reference to `amd_report_gart_errors'
amd64_edac.c:(.text+0x3e9b55): undefined reference to `amd_register_ecc_decoder'
drivers/built-in.o: In function `amd64_nbea_store':
amd64_edac_dbg.c:(.text+0x3ea22e): undefined reference to `amd_decode_nb_mce'
drivers/built-in.o: In function `amd64_remove_one_instance':
amd64_edac.c:(.devexit.text+0x3eea): undefined reference to `amd_report_gart_errors'
amd64_edac.c:(.devexit.text+0x3ef6): undefined reference to `amd_unregister_ecc_decoder'
the AMD EDAC code has a dependency on CONFIG_CPU_SUP_AMD facilities. The
patch below solves the problem here.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
init_IRQ() and x86_late_time_init() are missing __init annotations.
The x86 platform ops variables are annotated, but the annotation needs
to be put between the variable name and the "=" of the initializer.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Add back FAIR_SLEEPERS and GENTLE_FAIR_SLEEPERS.
FAIR_SLEEPERS is the old logic: credit sleepers with their sleep time.
GENTLE_FAIR_SLEEPERS dampens this a bit: 50% of their sleep time gets
credited.
The hope here is to still give the benefits of fair-sleepers logic
(quick wakeups, etc.) while not allow them to have 100% of their
sleep time as if they were running.
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Use uX rather than uintX_t types for consistency.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
catas_reset() uses pointer to mlx4_priv, but mlx4_priv is not valid
after call mlx4_restart_one().
Signed-off-by: Vitaliy Gusev <vgusev@openvz.org>
Acked-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
I have recently came across a preemption imbalance detected by:
<4>huh, entered ffffffff80644630 with preempt_count 00000102, exited with 00000101?
<0>------------[ cut here ]------------
<2>kernel BUG at /usr/src/linux/kernel/timer.c:664!
<0>invalid opcode: 0000 [1] PREEMPT SMP
with ffffffff80644630 being inet_twdr_hangman().
This appeared after I enabled CONFIG_TCP_MD5SIG and played with it a
bit, so I looked at what might have caused it.
One thing that struck me as strange is tcp_twsk_destructor(), as it
calls tcp_put_md5sig_pool() -- which entails a put_cpu(), causing the
detected imbalance. Found on 2.6.23.9, but 2.6.31 is affected as well,
as far as I can tell.
Signed-off-by: Robert Varga <nite@hq.alert.sk>
Signed-off-by: David S. Miller <davem@davemloft.net>
And turn it on for NUMA and MC domains. This improves
locality in balancing decisions by keeping up to
capacity amount of tasks local before looking for idle
CPUs. (and twice the capacity if SD_POWERSAVINGS_BALANCE
is set.)
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
If qdisc_get_stab returns error in qdisc_create there is skipped qdisc
ops->destroy, which is necessary because it's after ops->init at the
moment, so memory leaks are quite probable.
Signed-off-by: Jarek Poplawski <jarkao2@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Fixes RMX problems on older Apple laptops which don't have an x86 BIOS ROM.
Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
This is necessary to get ftrace syscall tracing working again.. a fairly
trivial and mechanical change. The one benefit is that this can also be
enabled on sh64, despite not having its own ftrace port.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
When ftrace had issues with NMIs, it was needed to annotate all
the areas that kprobes had issues with notrace. Now that ftrace is
NMI safe, the functions that limit ftrace from tracing are just a
small few.
Kprobes is too big of a set for ftrace not to trace. Remove the
coupling.
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Many years ago when this driver was written, it had a use, but these
days it's nothing but trouble and distributions should not enable it
in any situation.
Pretty much every console device a sparc machine could see has a
bonafide real driver, making the PROM console hack unnecessary.
If any new device shows up, we should write a driver instead of
depending upon this crutch to save us. We've been able to take care
of this even when no chip documentation exists (sunxvr500, sunxvr2500)
so there are no excuses.
Signed-off-by: David S. Miller <davem@davemloft.net>
The good definition of CLOCK_TICK_RATE for coldfires has been lost in the
merge of m68k and m68knommu include files. Restore it. Culprit :
commit ebafc17468
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The ethernet pins on the 532x ColdFire CPU family are multi-function
pins. We need to enable them as ethernet pins when using the FEC
ethernet driver.
Bug report, and older patch, from timothee@manaud.net.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The improved interrupt support for ColdFire CPU cores means we no
longer need all the interrupt setup and ack hacks to support the NE2000
driver on ColdFire platforms. Remove all that code.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
There is really no limit to the addresses which can be used by the
in*() and out*() family of IO space calls in m68k non-MMU environments.
So don't impose an artificial address limit, allow the full 32bit range.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Now that the ColdFire 5272 has full interrupt controller functionality
we can remove all the interrupt masking and acking code from the FEC
ethernet driver.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The ColdFire 5272 CPU has a very different interrupt controller than
any of the other ColdFire parts. It needs its own controller code to
correctly setup and ack interrupts.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The ColdFire 5249 CPU has a second (compleletly different) interrupt
controller. It is the only ColdFire CPU that has this type. It controlls
GPIO interrupts amongst a number of interrupts from other internal
peripherals. Add support code for it.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The recent changes to the old ColdFire interrupt controller code means
we no longer need to manually unmask the timer interrupt. That is now
done in the interrupt controller code proper.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The newer ColdFire 532x family of CPU's uses the old timer, but has a
newer interrupt controller. It doesn't need the special timer setup
that was required when using the older interrupt controller. Remove the
dead timer irq and level setting code, and define the hard coded vector.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The ColdFire "timers" clock setup can be simplified. There is really no
need for the flexible per-platform setup code. The clock interrupt can be
hard defined per CPU platform (in CPU include files). This makes the
actual timer code simpler.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The external interrupts used on the old Coldfire parts with the old style
interrupt controller can be properly mask/unmasked in the interrupt
handling code.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Each of the ColdFire CPU platform code that used the old style interrupt
controller had its own copy of the mcf_autovector() function. They are all
the same, remove them all and create a single function in the common
coldfire/intc.c code.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Create an mcfintc.h include file with the definitions for the old style
ColdFire interrupt controller. They are only needed on CPU's that use
this old controller - so isolate them on their own.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The ColdFire intc-simr interrupt controller should mask off all
interrupt sources at init time. Doing it here instead of separately
in each platform setup.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
With fully implemented interrupt controller code we don't need to do
the custom interrupt setup for the timer device of the ColdFire 532x.
Remove that code.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
With proper interrupt controller code in place there is no need for
devices like the timers to have custom interrupt masking code.
Remove it (and the defines that go along with it).
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The new code for the interrupt controller in the ColdFire 520x takes
care of all the interrupt controller setup. No manual config of the
level registers (ICR) is required by the platform device setup code.
So remove it.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Each different m68knommu CPU interrupt controller type has its own
interrupt controller data structures now. Remove the old, and now not
used, common irq structs and init code from here.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Define the interrupt controller structures along with the interrupt
controller code for the 68360 CPU. This brings the interrupt setup
and control into one place for this CPU family.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Define the interrupt controller structures along with the interrupt
controller code for the 68328 CPU family. This brings the interrupt
setup and control into one place for this CPU family.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The old ColdFire CPU's (5206, 5307, 5407, 5249 etc) use a simple
interrupt controller. Use common setup code for them. This addition
means that all ColdFire CPU's now have some specific type of interrupt
controller code.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
With the common intc-simr interrupt controller code in place the ColdFire
532x family startup code can be greatly simplified. Remove all the
interrupt masking code, and the per-device interrupt config here.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
The ColdFire 532x family of parts uses 2 of the same INTC interrupt
controlers used in the ColdFire 520x family. So modify the code to
support both parts. The extra code for the second INTC controler in
the case of the 520x is easily optimized away to nothing.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
