This patch converts the leds-netxbig driver to use the devres functions
devm_gpio_request_one() and devm_led_classdev_register(). This allows to
simplify the code a bit.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Since DT support is now available for the LEDs found on the LaCie
netxbig boards (Kirkwood-based), then the old-fashion netxbig board
setup file is no longer needed. This patch removes this file.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
This patch adds DT entries for the LEDs found on the Kirkwood-based
LaCie boards 2Big and 5Big Network v2.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
This patch adds device tree support for the netxbig LEDs.
This also introduces a additionnal DT binding for the GPIO extension bus
(netxbig-gpio-ext) used to configure the LEDs. Since this bus could also
be used to control other devices, then it seems more suitable to have it
in a separate DT binding.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
This patch adds possibility to invert heartbeat blinking.
The inverted LED is more time ON then OFF. It's because it looks
better when the heartbeat LED is next to other LED which is most
time ON. The invert value is exported same way via sysfs in file
invert like oneshot. I get inspiration from this trigger.
Signed-off-by: Jiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Since the API for controlling LED brightness and blinking is defined in
the LED core, move the related timer and work callbacks to the led-core.c,
and initialize them through a new led_core_init API.
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Pavel Machek <pavel@ucw.cz>
Spaces at the starting of a line are removed, indentation using
tab, instead of space. Also, line width of more than 80 characters
is also taken care of.
Two warnings are left alone to aid better readability.
Signed-off-by: Muhammad Falak R Wani <falakreyaz@gmail.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Use of resource-managed function devm_led_classdev_register
instead of led_classdev_register is preferred, consequently
remove redundant function micro_leds_remove.
Signed-off-by: Muhammad Falak R Wani <falakreyaz@gmail.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Use resource-managed function devm_led_classdev_register
instead of led_classdev_register to make the error path simpler.
The goto is replaced with direct return, unneeded label err is
dropped. Also, remove redundant ot200_led_remove.
Signed-off-by: Muhammad Falak R Wani <falakreyaz@gmail.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Use resource-managed function devm_led_classdev_register
instead of led_classdev_register to simplify error path.
An unnecessary check of ret is replaced with a direct return
Also, remove redundant hp6xxled_remove.
Signed-off-by: Muhammad Falak R Wani <falakreyaz@gmail.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Use resource-managed function devm_led_classdev_register instead
of led_classdev_register to make the error-path simpler.
To be compatible with the change, goto is replaced with direct
return, unneeded label err_null is dropped and unnecessary variable
retval is removed. Also, remove redundant cobalt_qube_led_remove.
Signed-off-by: Vaishali Thakkar <vthakkar1994@gmail.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
- Vast improvements to gk20a instmem handling.
- Improved PGOB detection + GK107 support.
- Compatibility between old/new interfaces added, final missing piece to
finally enabling userspace to start using them.
- Kepler GDDR5 PLL stability improvements
- Support for non-GPIO (PWM) voltage controllers
- G8x/GT2xx memory clock improvements
- Misc other fixes
* 'linux-4.4' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (45 commits)
drm/nouveau: bump patchlevel to indicate availability of abi16/nvif interop
drm/nouveau/abi16: implement limited interoperability with usif/nvif
drm/nouveau/abi16: introduce locked variant of nouveau_abi16_get()
drm/nouveau/abi16: remove unused argument from nouveau_abi16_get()
drm/nouveau/pci: enable c800 magic for Medion Erazer X7827
drm/nouveau/pci: enable c800 magic for Lenovo Y510P
drm/nouveau/pll/gk104: fix PLL instability due to bad configuration with gddr5
drm/nouveau/clk/g84: Enable reclocking for GDDR3 G94-G200
drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristic
drm/nouveau/fb/ramnv50: Script changes for G94 and up
drm/nouveau/fb/ramnv50: Deal with cards without timing entries
drm/nouveau/fb/ramnv50: Voltage GPIOs
drm/nouveau/fb/ramgt215: Restructure r111100 calculation for DDR2
drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for it
drm/nouveau/fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to generic
drm/nouveau/bios/rammap: Identify DLLoff for >= GF100
drm/nouveau/pci: Handle 5-bit and 8-bit tag field
drm/nouveau/disp,pm: constify nvkm_object_func structures
drm/nouveau/gr: add FERMI_COMPUTE_B class to GF110+
drm/nouveau/gr: document mp error 0x10
...
This pull request includes comprehensive cleanups to HDMI part and
several fixups. In addition, this pull request includes also a defconfig
patch which enables mixer driver as default. For this, I got already
Acked-by from Krzysztof Kozlowski who is a Exynos SoC maintainer.
* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: (34 commits)
drm/exynos/gem: remove DMA-mapping hacks used for constructing page array
ARM: exynos_defconfig: enable Exynos DRM Mixer driver
drm/exynos: simplify Kconfig component names
drm/exynos: re-arrange Kconfig entries
drm/exynos: abstract out common dependency
drm/exynos: separate Mixer and HDMI drivers
drm/exynos/mixer: replace direct cross-driver call with drm mode validation
drm/exynos: add atomic_check callback to exynos_crtc
drm/exynos/decon5433: add support for DECON-TV
drm/exynos/decon5433: remove duplicated initialization
drm/exynos/decon5433: merge different flag fields
drm/exynos/decon5433: add function to set particular register bits
drm/exynos/decon5433: fix timing registers writes
drm/exynos/decon5433: add PCLK clock
drm/exynos: cleanup name of gem object for exynos_drm
drm/exynos: fix to detach device of iommu
drm/exynos: add cursor plane support
drm/exynos: add global macro for the default primary plane
drm/exynos: fix spelling errors
drm: exynos: mixer: fix using usleep() in atomic context
...
USIF already takes the client mutex, but will need access to ABI16 data
in order to provide some limited interoperability.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This patch uses an approach closer to the nvidia driver to configure
both PLLs for high gddr5 memory clocks (usually above 2400MHz)
Previously nouveau used the one PLL as it was used for the lower clocks
and just adjusted the second PLL to get as close as possible to the
requested clock. This means for my card, that I got a 4050 MHz clock
although 4008 MHz was requested.
Now the driver iterates over a list of PLL configuration also used by
the nvidia driver and then adjust the second PLL to get near the
requested clock. Also it hold to some restriction I found while
analyzing the PLL configurations
This won't fix all gddr5 high clock issues itself, but it should be
fine on hybrid gpu systems as found on many laptops these days. Also
switching while normal desktop usage should be a lot more stable than
before.
v2: move the pll code into ramgk104
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Your milage may vary, as it's only been tested on a single G94 and one G96.
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Avoids waiting for VBLANKS that never arrive on headless or otherwise
unconventional set-ups. Strategy taken from MEMX.
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10053c is not even read on some cards, and I have no idea exactly what the
criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables
all features that are never used. The practical effect should be the same
as this implementation though.
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Like Pierre's G94. We might want to structure Kepler similarly in a follow-up.
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Does not seem to be necessary for NVA0, hence untested by me.
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Seems to be mostly equal to DDR3 on < GT218, should improve stability for
DDR2 reclocks.
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
In preparation of changing FBVDDQ, as observed on at least one GDDR3 card.
While at it, adhere to func.log[1] properly for consistency.
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
If the hardware supports extended tag field (8-bit ones), then enable it.
This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).
In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.
Fixes: fdo#86537
v2: Restrict changes to chipsets >= 0x84
v3:
* Add nvkm_pci_mask to pci.h
* Mask bit 8 before setting it
v4:
* Rename `add` argument of nvkm_pci_mask to `value`
* Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
checks
v5:
* Rebase code on latest PCI structure
* Restore PCIe check
* Fix namings in nvkm_pci_mask
* Rephrase part of the commit message
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
These nvkm_object_func structures are never modified. All other
nvkm_object_func structures are declared as const.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
GF110+ supports both the A and B compute classes, make sure to accept
both.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE,
which apparently happens when trying to use an atomic operation on
local or shared memory (instead of global memory).
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
If pm_runtime_get_sync() we were going to "out" but we missed freeing
vma.
Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
coverity.com reported that memset was using a buffer of size 0, on
checking the code it turned out that the function was not being used. So
remove it.
Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Was not able to obtain a trace of NVRM due to kernel version annoyances,
however, experimentally confirmed that the WAR we use on NV50/G8x boards
works here too.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.
This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
I got confirmation that we can read and change the voltage with the same code.
The divider is also computed correctly on the gm204 we got our hands on.
Thanks to Yoshimo on IRC for executing the tests on his gm204!
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Let's ignore the other desktop Maxwells until I get my hands on one and confirm
that we still can change the voltage.
Signed-off-by: Martin Peres <martin.peres@free.fr>
Most Keplers actually use the GPIO-based voltage management instead of the new
PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles
the case where no GPIOs exist.
All the Maxwells seem to use the PWM method though.
v2:
- Do not forget to commit the PWM configuration change!
Signed-off-by: Martin Peres <martin.peres@free.fr>
This patch is not ideal but it definitely beats a rewrite of the current
interface and is very self-contained.
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
So far the DMA mask was not set for platform devices, which limited them
to a 32-bit physical space. Allow dma_set_mask() to be called for
non-PCI devices, and also take the IOMMU bit into account since it could
restrict the physically addressable space.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
