Add processor identifiers for single core and multi-core
proAptiv processors.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6133/
For MIPS32R3 supported cores, the EHINV bit needs to be set when
invalidating the TLB. This is necessary because the legacy software
method of representing an invalid TLB entry using an unmapped address
value is not guaranteed to work.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6132/
MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
New Aptiv cores support the TLBINVF instruction for flushing
the VTLB.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6130/
The UNIQUE_ENTRYHI definition was duplicated whenever there
was the need to flush the TLB entries. We move this common
definition to a header file.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6129/
Add support for including VPE and TC ids in /proc/cpuinfo output as
appropriate when MT/SMTC is enabled.
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6065/
Commit 225ae5fd9a
"MIPS: Malta: Fix interupt number of CBUS UART"
fixed the IRQ number for the ttyS2 CBUS UART. However, this now
conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta
interrupt code arbitrarily binds IPIs to INT2 and INT3 and since
ttyS2 uses the INT2 IRQ line, closing the device disables the
INT2 interrupt and this effectively disables the IPI1 interrupt
as well. This patch is mainly a workaround until the Malta code
is fixed properly.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6045/
The cacheer register is always implemented in the same way in the
MIPS32r2 Imgtec cores so print the ES bit when an cache error
occurs.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6041/
If GIC is present, then use it to send IPIs between the cores.
Using GIC for IPIs is simpler and is usable for multicore
systems compared to the existing way of doing IPIs where all VPEs
had to be disabled for another VPE to access the Cause register
in one of the TCs and enable all the VPEs back.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6040/
According to Documentation/cpu-hotplug.txt, the cpu_present_mask should
contain all the CPUs which are present in the system. Therefore, all the TCs
currently present in the system should be marked as 'present' even if they
will never be brought online.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6039/
According to MIPS32 and MIPS64 PRA documents,
a value of 7 in IL and DL fields is marked as "Reserved"
so panic if the core uses this value in the config1 register.
Also simplify the code a little bit.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5861/
The mips_mt_* symbols are only built and exported if
CONFIG_MIPS_MT is enabled.
Fixes the following build problem when CONFIG_SMP is enabled
but CONFIG_MIPS_MT is not.
arch/mips/built-in.o: In function `cmp_prepare_cpus':
arch/mips/kernel/smp-cmp.c:197:
undefined reference to `mips_mt_set_cpuoptions'
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5860/
Fix nvram_read_alpha2 copying too many bytes over the ssb_sprom
structure. Also fix the arguments of the read_macaddr, although the code
was technically not wrong before due to an extra dereference.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6211/
This adds support for vectored interrupt which is supported by the SoC
using a MIPS 74K CPU like the BCM4716 and BCM4706.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6290/
The BCM47XX SoC code missed a cpu-feature-overrides.h header file, this
patch adds it. This code supports a long line of SoCs with different
features so for some features we still have to rely on the runtime
detection.
This was crated by checking the features of a BCM4712, BCM4704,
BCM5354, BCM4716 and BCM4706 SoC and then tested on these SoCs. There
are some SoCs missing but I hope they do not have any more or less
features.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6289/
Move the possible nvram sizes from the stack into the data segment
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6044/
plat_irq_dispatch() is called from asm code, add asmlinkage.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6043/
The defconfig for bcm47xx contained lots of driver which are not
special for these SoCs and missed on the other side some some drivers
for parts essential for these SoC and only found on here. The flash,
usb and some Ethernet driver were missing.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5930/
The BCM47xx SoCs have a 8250 serial compatible console at address
0x18000300 and an other at 0x18000400. On most devices 0x18000300 is
wired to some pins on the board, we should use that.
This is the smae for the AI (bcma) and the SB (ssb) bus, this is some
offset on the chip common core.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5889/
bcm47xx only uses the CFE code for early print to a console, but that
is also possible with a early print serial 8250 driver.
The CFE api init causes hangs somewhere in prom_init_cfe() on some
devices like the Buffalo WHR-HP-G54 and the Asus WL-520GU.
This was reported in https://dev.openwrt.org/ticket/4061 and
https://forum.openwrt.org/viewtopic.php?id=17063
This will remove all the CFE handling code from bcm47xx.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5888/
Recently the output of "system type" in /proc/cpuinfo was changed to
Broadcom BCM4730 (Some sample board), but it is better to just print
the SoC name in the "system type" entry. The board name will be added
in the machine entry later.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5865/
All MIPS cores on BCM63XX identify as Broadcom, not MIPS, so no need
to support non-broadcom MIPS CPUs. This also ensures that CPU_BMIPS
is always selected.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6246/
BMIPS32 and BMIPS3300 also need to be available for MIPS32R1, as
bcm47xx might not select BMIPS.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6245/
Let BCM47XX_SSB select the appropriate BMIPS CPUs enountered on those
systems.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6244/
Let each supported chip select the appropirate SYS_HAS_CPU_BMIPS*
option for its embedded processor, so support will be conditionally
included.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6250/
Use the return value for guarding further SMP setup.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6249/
Add a helper similar to the generic register_XXX_smp_ops() for bmips.
Register SMP UP ops in case of BMIPS32/3300.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6248/
Codewise there is no difference between these two, so it does not make
sense to treat them differently. Also chip families having one of these
tend to have the other.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6247/
As they are MIPS32 CPUs they do support the prefetch opcode.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6243/
All BMIPS CPUs support HIGHMEM, so it should be selected by CPU_BMIPS.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6242/
Instead of treating each flavour as an exclusive CPU to select, make
BMIPS the only option and let SYS_HAS_CPU_BMIPS* decide for which
flavours to include support.
Run tested on BMIPS3300 and BMIPS4350, only build tested for BMIPS4380
and BMIPS5000.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6240/
Allow building for all bmips cpus at the same time by changing ifdefs
to checks for the cpu type, or adding appropriate checks to the
assembly.
Since BMIPS43XX and BMIPS5000 require different IPI implementations,
split the SMP ops into one for each, so the runtime overhead is only
at registration time for them.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6241/
Add guards around the enum to allow including cpu.h from assembly.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6238/
BCM3368 has the same shared TLB as BCM6358.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6239/
Properly set up the HSSPI clock rate depending on the SoC's PLL rate.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6177/
open/release operations require userspace transitions to keep track
of the open count and to perform any FS-specific setup. However,
for some purely read-only FSs which don't need to perform any setup
at open/release time, we can avoid the performance overhead of
calling into userspace for open/release calls.
This patch adds the necessary support to the fuse kernel modules to prevent
open/release operations from hitting in userspace. When the client returns
ENOSYS, we avoid sending the subsequent release to userspace, and also
remember this so that future opens also don't trigger a userspace
operation.
Signed-off-by: Miklos Szeredi <mszeredi@suse.cz>
Various read operations (e.g. readlink, readdir) invalidate the cached
attrs for atime changes. This patch adds a new function
'fuse_invalidate_atime', which checks for a read-only super block and
avoids the attr invalidation in that case.
Signed-off-by: Andrew Gallagher <andrewjcg@fb.com>
Signed-off-by: Miklos Szeredi <mszeredi@suse.cz>
As noticed by Coverity the "num != 0" condition never triggers. Instead it
should check for a complete page.
Signed-off-by: Miklos Szeredi <mszeredi@suse.cz>
Having this struct in module memory could Oops when if the module is
unloaded while the buffer still persists in a pipe.
Since sock_pipe_buf_ops is essentially the same as fuse_dev_pipe_buf_steal
merge them into nosteal_pipe_buf_ops (this is the same as
default_pipe_buf_ops except stealing the page from the buffer is not
allowed).
Reported-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Miklos Szeredi <mszeredi@suse.cz>
Cc: stable@vger.kernel.org
With b8668fd0a7 "s390/uapi: change struct statfs[64] member types
to unsigned values" the size of a couple of struct statfs64 member got
incorrectly changed from 64 to 32 bit for 32 bit builds.
Fix this by changing the type of couple of struct statfs64 members from
unsigned long to unsigned long long.
The definition of struct compat_statfs64 was correct however.
Cc: stable@vger.kernel.org # v3.10+
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Remove some dead uaccess extern declarations and also make some functions
static, since they are only used locally.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
If get_fs() == USER_DS we better test if current->mm is not zero before
walking page tables.
The page table walk code would try to lock mm->page_table_lock, however
if mm is zero this might crash.
Now it is arguably incorrect trying to access userspace if current->mm
is zero, however we have seen that and s390 would be the only architecture
which would crash in such a case.
So we better make the page table walk code a bit more robust and report
always a fault instead.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Get rid of this link error:
arch/s390/built-in.o: In function `smp_prepare_cpus':
(.init.text+0x301e): undefined reference to `dump_save_area_create'
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
