This implements UEFI kernel support for 32-bit ARM, based on the existing
arm64 support and existing generic early ioremap support. It is based on
commit f7d9248942 ("arm64/efi: refactor EFI init and runtime code for
reuse by 32-bit ARM"), which was pulled from the arm64 repo [1] as branch
'aarch64/efi'
[1] git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
This patch set fixes the node names of X-Gene I2C, GPIO
controller DT nodes; and also removes I2C clock nodes as
the same clock is shared between 2 I2C controllers
on X-Gene SoC.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWhGzxAAoJEB11UG/BVQ/gkEgP/izhZ6sSTqOmRP4+M0WHAvAL
q2Jsth3FWCLJWu5rMjQsWK/cfCr/bA8mqfZvMsTjOMBkDPBjOR+k25g/kdTN1ltI
dzA8I12xJAqFyTilTjb/xHWhDcSZxzrqR6bVTCtI+CRxhhMm9tJC4z8FAMjhHTev
ugxKZ/9ANloG/PQ3GT+GPXQzC0PwfN8j9io5iaWmnqvs/GNk8yb9hgK7wXSVMGm7
0Nj8no1cBI3J/3ZNWCsh+o+f3nZsC7mi9NaMJdGDeiSqp1YPBY5WPn6txIoG1LYF
zN8866Yow2ppo9W7dl9/JJkidyb2+hXtsNl33QZHiupbmbLc1o6I1RGbWqw7rb8o
s4Lt4GD8gULaKXXHi9YmFA7Y5aWKrnozxnmBMITtGcOyZ6YicL39/cd6FUYGs7EJ
a/fhmoG3YzVXTy2tDE9s6ux2WQ5GnahWO0s5dBGx+S6oz1bfVumtRI+iSScrZ7a+
+ODa6OeYk6fGJpB6lN8oafSKA2lTN5sVv60XJ/t5uYQ+5ihy3wNx4u1y3rXg5RCt
RhfI54Gm5YeAhQJwrNKX5RfxR5hGwg2oheL1qXI3wfhgHLyJCHqpitV8WNdOOjOC
7irlc2iQfe+N0ReN+IAUvNBHJEm8C6xYEz1LogBscSacFHZ7V9+1+MO7y5y1YQSd
2YWPv3xPPRTv3+Q2th5d
=7pR3
-----END PGP SIGNATURE-----
Merge tag 'xgene-dts-fixes-for-v4.5' of https://github.com/AppliedMicro/xgene-next into next/dt64
Merge "Fixes for X-Gene DTS for v4.5" from Duc Dang:
This patch set fixes the node names of X-Gene I2C, GPIO
controller DT nodes; and also removes I2C clock nodes as
the same clock is shared between 2 I2C controllers
on X-Gene SoC.
* tag 'xgene-dts-fixes-for-v4.5' of https://github.com/AppliedMicro/xgene-next:
arm64: dts: X-Gene v2: I2C1 clock is always on
arm64: dts: X-Gene v1: I2C0 clock is always on
arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms
This patch updates the LS2080a DTSI (DTS Include) file to add
support for eight SP805 Watchdog units which can be used to
reset the eight Cortex-A57 cores available on LS2080A.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
X-Gene v2 I2C0 and I2C1 controllers share the same clock
enable register field. This patch remove clock node for I2C1
and leave I2C1 clock always on as having it toggled on/off
will affect I2C0 operation.
Signed-off-by: Duc Dang <dhdang@apm.com>
X-Gene v1 I2C0 and I2C1 controllers share the same clock
enable register field. This patch remove clock node for I2C0
and leave I2C0 clock always on as having it toggled on/off
will affect I2C1 operation.
Signed-off-by: Duc Dang <dhdang@apm.com>
Use devicetree standard node name for I2C (i2c@...),
GFC GPIO (gpio@...), DW GPIO (gpio@...), Standby GPIO (gpio@...).
The DT node name of USB (dwusb@...) still needs to be kept to
maintain backward compatibility with old firmware.
Signed-off-by: Duc Dang <dhdang@apm.com>
a regulator voltage and a typo fix.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJWd005AAoJEPOmecmc0R2BT1cH/AtopgXkiguqobWz/tHhaz/T
OHETYVDzISgp4w/FnpugPollw4LhLkC4JkA7Sr41tNZzIq2loqSW1f94ige1Qmfo
dtt/eUr9ULN3GAa3b1sUbK7W/slw3zt7o2TggEG375BsubQagyVNE2P28j9vIArr
XL+XsekAGnj46MwvP/1Wro/fm6wUWZJV22itIBllZnQoTm51CjmzXajAeO1p4pxx
/K9pc+twcEjk2IoIWmn9gLLUC96HsQDCxU8lo74Ywiz9B5GZ+JFIJLAGjwAmPLei
O66yl/gnzJlszt09L0p6MqwzavJhVX80xcWiBdEKj8FRjOeSvfn7nnuYt5sPb6s=
=zB/I
-----END PGP SIGNATURE-----
Merge tag 'v4.5-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
New node for the broadcast-timer of the rk3368, a non-critical fix for
a regulator voltage and a typo fix.
* tag 'v4.5-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add the broadcast-timer for RK3368 SoC
arm64: dts: rockchip: Fix typo in rk3368 sdmmc card detect pin name
arm64: dts: rockchip: correct voltage range for rk3368-evb-act8846 board
Signed-off-by: Olof Johansson <olof@lixom.net>
does not boot.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJWdxa8AAoJELQ5Ylss8dNDVxMP/iXCSr5/l9o20YihFvMopONT
KZ+u9rqhjV9rWN/IDi+Y+DwZnuK5s0xVsBPsHaNIZ+bJApjRVdpo9K5UyXFExlvX
EBmRFYpw/D8XqCkO/ijlWU2wrqL63Wa6zAIQOqBUTzEP+YlFi2S+GUGqq2QrxEza
t/WsP5KR258xzHYw/HE+qVX+idlp/4uYTF2/UvcHpFhW3DCfMIJCpj/sj5pEMd7n
hkw69wTejSd1gf+NgOibqKtS7ds3/tm1mDkdJgMqkqHUUtU0UPXwGBGnyxS6NUDl
Az9FhjTpBR006DIrYKsBsxzKUnTcVeRdsEPRzbRkcC7E2eWnA8ycazqP9pJG1NG6
OR52O2uBaGiDMpUO4qre1gRkQLTC7qV/91/YNitI+J1qxjHmkLhV9cfx+mpmJwDT
HAtkY7Ozq6zMRvGSprypbfl49HImebg2eGPsMWE6AIe/9lDp8aOYaBXjWU+/nynt
7FQCE2WtXDpFI9CHWOQy+hK/Mw5cu1DtSL7nxqVLm6LQ5CEdx5FvTDn2bzk7ox3c
pgGY6eQf/XzA+pNxCYMIF/bbv2oOtqK+GaZsriUrmMQeMhxcZKTMC03RGLyl/Ccm
g+eY0z4r8w2o0BIWdrVNTaSOcD8mz2vavxO1nV+YLO1K2cahoEQq3AnivnRaV+fl
Ow9K1GvfNeYhPf2TnzXx
=uTZJ
-----END PGP SIGNATURE-----
Merge tag 'v4.4-next-kconfig' of https://github.com/mbgg/linux-mediatek into next/config64
Enable mediatek clocksource driver by default as otherwise the system
does not boot.
* tag 'v4.4-next-kconfig' of https://github.com/mbgg/linux-mediatek:
arm64: mediatek: enable MTK_TIMER
Signed-off-by: Olof Johansson <olof@lixom.net>
Move the include of the reset contoller to include/dt-bindings/reset.
Add basic support for mt2701 SoC and evaluation board.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJWdxfdAAoJELQ5Ylss8dNDxEgP/RhO5qFNw7ThTlVd8HHHGXqu
JuUy8WsVsp5cPq1Aksf9qNYlkv3tdGtKDmVv1QDTg5lIB7ytrm6uO3m+4feM+Awk
6qya8meRQowZTBU9SoBMLiNvKSiHkHnGeXVW3br92cPK9uxNJlCU9M1y9h9T7siW
OdxQ884c09/ubTgUnspDPIrpoCCjcLvHhy+6etEfU6zZLxxOrOUbCFkOHxf4EHwZ
BVDgukpxlDb3yL+GX9S0IfZu7EDu7MnUx/14RqyEPeAdXG4GR+cLrVg5s0YYyLuI
YTRcwd7/WClMhGIYprf0mX8kPGJKC/L5JK7DGu1GmdLMCZ+vke5xgdqIiK0ssxkH
O8VJIWRL1W6OuJQpZUDxRGpMo0aR+0fhpR5FuAtCyM8kaq8zTT182SpXR1AgsYmD
FF8L6bxX68YIY8PHCs0B6wjN6gKGcQdXVPMAvPlLLaGbw5qZtLqiM2zQnaZSD6JM
9IpNx3jjjIWNHLol3wOQnosECJONqa/JuiWyCOA/5mGRAJS+NE7tEEnm9yTPrc3M
7dn4RrYq50xf0roqLpAmFZ6MU7RVA31vn0DkFnmRvoEzt5ZLAUMsg2nJImyhhMrm
f5cdYIumHQCT0lpSvZL8gL/D+7AIffQaaQIfXzb7TsvJuta2kJSNhEbV1gNxS5Bs
iPSJYeaMLhq807UJG+lw
=qUem
-----END PGP SIGNATURE-----
Merge tag 'v4.4-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt
Add regulators to the scpsys binding.
Move the include of the reset contoller to include/dt-bindings/reset.
Add basic support for mt2701 SoC and evaluation board.
* tag 'v4.4-next-dts' of https://github.com/mbgg/linux-mediatek:
dt-bindings: soc: Add supplies for Mediatek SCPSYS unit
ARM: mediatek: DT: Move reset controller constants into common location
ARM: dts: mediatek: add MT2701 basic support
Document: DT: Add bindings for mediatek MT2701 SoC Platform
Signed-off-by: Olof Johansson <olof@lixom.net>
* Enable SATA
* Add salvator-x part number to DT bindings documentation
* Enable all four A57 cores instead of just one
* Enhanced audio support:
- Use CS2000 as AUDIO_CLK_B
- Set ak4613 In/Out pin as single-end
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWc12aAAoJENfPZGlqN0++N7YP/iUOSo2pptyYMC6SYjT+v7ST
R2eYynCqUktGycOeMbxZzcm15jhltCE4roxz01uhuSETAHpBDCyMhr34075UCYr/
he/NoswZ2zFE9b2cKx6i0teb8Plegx3BJhBAovTK3kegEAg5ouqRX2Kyfa3/VWDd
ZoXXp2WiEQ09JVrJQGViCNb7EkKt2X3lFwctFWWMuR5dq2g12W4Ka2vbHNcBrWU8
otSAn7CFoEaKc190RF8kVcHPvVh87ZnuIW15Hs+fr5RFvnGy5PVOLF/l0/ihY9pF
ErP+M7G8s0wmh3OaeMWHXLeU2pY2TNWAY+mVo49TOe9HpTyC4ij0rDTHE9qiZELm
lwFP4Pl6liYnJzuAEYh9lbwbtkQ0jvjMihz7bhdlfXOaTFSjbev48NWh+HXeAlSv
LPCrukqKn1KQVNA2bU1Fg0mEpfpVy+42WAMm7dZzIEacOGs8/0khWZMl3rAvEiRT
EC4N/bVgIbspSTtvj4F6YHPhTnvI1kx9J5tbjDelTHwuxDBXwEGEiP6b3rTw3znL
xMv5hc+7kt77UHhmUCYZYpcKfiR8/6Rc8WiQaIdO2oglWdzKuaaf16Ib67aKj31D
y7SWpEyhUF9g/tqEUwmrL6Kl1F9EXKtYQh8rP2SaTWdU1Ndapa3mtRC95rxcpYai
ASSssEwMGwbS2S4Oui9G
=qm/m
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-dt3-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Third Round of Renesas ARM64 Based SoC DT Updates for v4.5
* Enable SATA
* Add salvator-x part number to DT bindings documentation
* Enable all four A57 cores instead of just one
* Enhanced audio support:
- Use CS2000 as AUDIO_CLK_B
- Set ak4613 In/Out pin as single-end
* tag 'renesas-arm64-dt3-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: renesas: r8a7795: fix SATA clock assignment
arm64: dts: salvator-x: Enable SATA controller
arm64: dts: r8a7795: Add SATA controller node
arm64: renesas: r8a7795: add internal delay for i2c IPs
arm64: renesas: salvator-x: Add board part number to DT bindings
arm64: dts: r8a7795: Add pmu device nodes
arm64: dts: r8a7795: Add Cortex-A57 CPU cores
arm64: dts: r8a7795: Add PSCI node
arm64: renesas: salvator-x: use CS2000 as AUDIO_CLK_B
arm64: renesas: salvator-x: set ak4613 In/Out pin as single-end
Signed-off-by: Olof Johansson <olof@lixom.net>
* Enable CS2000 and Renesas R-Car SATA driver
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWc1zcAAoJENfPZGlqN0++GKMP/RBwpAkn8GtGwmGEbIHmx0n7
npLr8+Anzt+jud6v5E17mg8k/7UDlCB+Deua366mpiAZ3KYNwEyViYXU0OwBwVMG
UbATErlvHVT9O/yD5z52hy+qSVlh2YhmhV55uQ7Ky5POpHWBazqFQqMdCLyDC8jU
qQBZpJ9i3pVc+N7+KvIUP1UPun4/5TcTy3sG+ZdTSZ4bCa6WGdKLR+hPzMXbm7Yv
v6dG+8yi8/4Xl2AT9brhg5v59KBKZM7bx6fSlPr7z09fhVadCjxjCMMGEKP+Q87I
nS2lB0mJ/5wNpZmZogzTOwTtiFgfDq4v082gA8MpydXsw787N9bXslMGq+V54xBB
QV0IxN/Tb8TXIgzDiN5/V5Oqh+nm1YfON/prI433H+itEFCXUIKhcO7vBExyRniw
RZfkF7BhvYHpOTBcCgfIvHhXKCrpliyan5bBS8/ADkngJJ56wO4AWSdi4vz9/P70
vqPDGfyiffOiXYGkr95AmQhSO6LOo/INmqAHhLb0Z65kVkIAAIiWvXmmxhNFhj9p
s4lMh6T0dK1PN2l/ctudgSIHgllQanJ5Vl7nPsHQTZ06lkW/O4gNxm3AtIlSRetN
/NaSrKVVmAIfCKwJ2VMZzVHruyYKJCTGkozW5QMtYh+zqbGyoxZ5R95BYA6R7Dq7
Bs8XsleUxMNJbk+ahpCX
=9272
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-defconfig3-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/config64
Third Round of Renesas ARM64 Based SoC Defconfig Updates for v4.5
* Enable CS2000 and Renesas R-Car SATA driver
* tag 'renesas-arm64-defconfig3-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: defconfig: add CS2000 support
arm64: defconfig: Add Renesas R-Car SATA driver for R-Car Gen3 SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
* Add fixed rate oscillators to dts
* Fixup PMIC alias and properties
* Change 8916-MTP compatible to be compliant with new scheme
* Fix 8x16 UART pinctrl configuration
* Add SMEM, RPM/SMD, and PM8916 support on MSM8916
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWckTvAAoJEFKiBbHx2RXVAH0QAIOVo46P/LtOQk8J+A8lUyM3
eui/kuJG5H9iKf+r7maPCnWQbkdRfAevHFBixDfqq3WLK6muNAsWlAeTWasBG2AR
mMqg/0pkVCJHHxJ9xeMqdo7RkAPDgmk/CiR+kD+SA19N+OegU+fExI7RyEd9LQ/B
sQgbebZxB5VBQPIPlJorFP4UPG6T/sbV4FjsQ65GMGxZ321EV4OsApJHbEK9bzO7
8fFAU6OX9wRcqkQ9K5aLTo312ZzE1TvgyPLfSfZmAVAmgrWSC99nqKzd3u1qeCOC
jAzcv9yGMx4bfCMZcTuHp2OIGHbxFE9S0vBHfZrlzYxn8gniKBepGIr8w09TZgEq
TfDl2pzzfOsLF2sh1UAA3Is/i88zgf/EXt4q+1qgSZAGG66BvNUHDZP3uXVItRcY
GvugxN/96v5eszrG/0d+0IYQzYvFqXAbFfuYi5ax4+B4eah5YNPjSufJnWbHKogt
Eg3DVnvlilMBDpqc8zMCR5AnLsFFxGZEtsd8WTofE3Gd8wtkqCMS95Hh5PkNxkyC
bp1WXKEarMPjJ0X3YtAhQo7M5eFMYsZPxblhCr1CPmuVFzbwlyMkpqdaX23H93Ni
it+geo3aRKFdtxIX11bqCO6S6f2en7ZGg1bsychxqk+oN309EAqJkQAyNGYpo2h3
aWGLpsxVEC3/NHNh9aRg
=mu4g
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64
Qualcomm ARM64 Updates for v4.5
* Add fixed rate oscillators to dts
* Fixup PMIC alias and properties
* Change 8916-MTP compatible to be compliant with new scheme
* Fix 8x16 UART pinctrl configuration
* Add SMEM, RPM/SMD, and PM8916 support on MSM8916
* tag 'qcom-arm64-for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: Add PM8916 support on MSM8916
arm64: dts: qcom: Add RPM/SMD support on MSM8916
arm64: dts: qcom: Add MSM8916 SMEM nodes
arm64: dts: set the default i2c pin drive strength to 16mA
arm64: dts: fix the i2c aliasing to match to schematics.
arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators
arm64: dts: qcom: Alias pm8916 on msm8916 devices
arm64: dts: qcom: Make msm8916-mtp compatible string compliant
arm64: dts: qcom: 8x16: UART1 and UART2 use DMA for RX and TX
arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations
Signed-off-by: Olof Johansson <olof@lixom.net>
This set of patches enable various drivers and features required by
64-bit Tegra SoCs (Tegra132 and Tegra210).
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJWcqwyAAoJEN0jrNd/PrOh8k0QAJuMMfICxDzPRCWZ+I13o/Pk
RHlu+ISgOEO5wiCoLsQha628OXu8pl5MiGtD1I84c5DStCF++2SH3aZz3XDaiXEq
ew19o7lPbvhr2XfHeLMy9DxxYCBgFpKwgNFQanUE5pIs9GFUPuCKAbGkuvFOXKTO
XV527jxg/TMXNqHkGGiChHjy6AzhVQ69JTsclERikQ9JOspihl3SgXwqagEvmlEy
ngaxwihDtJ/H+Jw5JhjYEFyA6io998lXlBKriLsu3xbE0SnqH3BU6MBOMNIiqOBB
SwZdyE7Q8hS18mQg9aqxVZNdYaLDhMyjNLliZ3TnYJFe/MsyVtn1gvebEBiWxwT1
f0GtT8Z1iAaE3RFlNT2+Da77rCdPYP2VJSmTN655rVFqmHmWksTQeud7TUyZ6BvM
c7L1XQlG6SWVEbP9XiAbjerj/nqw6YOM7Orde2WvkrwSO97pzT2ACtorgh0Ak5ng
vL29O4eOduq0vJV6eMXX7LulO/7VIO39aNbG1x6V1fh1LK7QGzmBlXc0f/HbNl8o
Z6U3Qe8SoeGxRUfavX3lrhj1sqB6kgaheMmAKHLZUJuTDXq6i73bss0Cnl6wkRPp
8Lh6jqITWBCXj8/NqBPBQ1iei95x3qF7F1FxmD8rh02xBZDGPXHswxbO7lbH77Al
u3LApmgvYfeuIaPyiu/y
=e72e
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.5-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/config64
ARM: tegra: Default configuration updates for v4.5-rc1
This set of patches enable various drivers and features required by
64-bit Tegra SoCs (Tegra132 and Tegra210).
* tag 'tegra-for-4.5-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Enable printk timestamps
arm64: defconfig: Enable squashfs support
arm64: defconfig: Enable sdhci-tegra driver
arm64: defconfig: Enable serial-tegra driver
arm64: defconfig: Enable tegra-apbdma driver
arm64: defconfig: Do not disable Tegra AHB driver
arm64: defconfig: Enable Tegra210 support
Signed-off-by: Olof Johansson <olof@lixom.net>
Add label properties to provide a way to identify UARTs based on their
board or connector name. This follows naming convention in 96boards CE
spec. Ports without external connections are not labelled.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add label properties to provide a way to identify UART, I2C and SPI
ports based on their connector names. This follows naming convention in
96boards CE spec. Ports without external connections are not labelled.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Andy Gross <agross@codeaurora.org>
Acked-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
The LS UART0 is not used by anything else and should be enabled for
expansion boards.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Andy Gross <agross@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds idle-states bindings data collected through a set of
benchmarking experiments (latency and energy consumption) on Juno
boards. Latencies data represents the worst case scenarios as required
by the DT idle-states bindings.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Added sys-reboot node to the FSL's LS2080A SoC DT to leverage
the ARM-generic reboot mechanism for this SoC. This mechanism
is enabled through CONFIG_POWER_RESET_SYSCON.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks are
similar to LS1021a which also complies to Freescale Chassis 2.1 spec.
Created LS1043a SoC DTSI file to be included by board level DTS files.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Cortex-A72 has a PMUv3 implementation that is compatible with the PMU
implemented by Cortex-A57.
This patch hooks up the new compatible string so that the Cortex-A57
event mappings are used.
Signed-off-by: Will Deacon <will.deacon@arm.com>
It's all very well providing an events directory to userspace that
details our events in terms of "event=0xNN", but if we don't define how
to encode the "event" field in the perf attr.config, then it's a waste
of time.
This patch adds a single format entry to describe that the event field
occupies the bottom 10 bits of our config field on ARMv8 (PMUv3).
Signed-off-by: Will Deacon <will.deacon@arm.com>
This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit ac7b406c1a ("arm64: Use pr_* instead of printk") was a fairly
mindless s/printk/pr_*/ change driven by a complaint from checkpatch.
As is usual with such changes, this has led to some odd behaviour on
arm64:
* syslog now picks up the "pr_emerg" line from dump_backtrace, but not
the actual trace, which leads to a bunch of "kernel:Call trace:"
lines in the log
* __{pte,pmd,pgd}_error print at KERN_CRIT, as opposed to KERN_ERR
which is used by other architectures.
This patch restores the original printk behaviour for dump_backtrace
and downgrade the pgtable error macros to KERN_ERR.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Function graph tracer modifies a return address (LR) in a stack frame
to hook a function return. This will result in many useless entries
(return_to_handler) showing up in
a) a stack tracer's output
b) perf call graph (with perf record -g)
c) dump_backtrace (at panic et al.)
For example, in case of a),
$ echo function_graph > /sys/kernel/debug/tracing/current_tracer
$ echo 1 > /proc/sys/kernel/stack_trace_enabled
$ cat /sys/kernel/debug/tracing/stack_trace
Depth Size Location (54 entries)
----- ---- --------
0) 4504 16 gic_raise_softirq+0x28/0x150
1) 4488 80 smp_cross_call+0x38/0xb8
2) 4408 48 return_to_handler+0x0/0x40
3) 4360 32 return_to_handler+0x0/0x40
...
In case of b),
$ echo function_graph > /sys/kernel/debug/tracing/current_tracer
$ perf record -e mem:XXX:x -ag -- sleep 10
$ perf report
...
| | |--0.22%-- 0x550f8
| | | 0x10888
| | | el0_svc_naked
| | | sys_openat
| | | return_to_handler
| | | return_to_handler
...
In case of c),
$ echo function_graph > /sys/kernel/debug/tracing/current_tracer
$ echo c > /proc/sysrq-trigger
...
Call trace:
[<ffffffc00044d3ac>] sysrq_handle_crash+0x24/0x30
[<ffffffc000092250>] return_to_handler+0x0/0x40
[<ffffffc000092250>] return_to_handler+0x0/0x40
...
This patch replaces such entries with real addresses preserved in
current->ret_stack[] at unwind_frame(). This way, we can cover all
the cases.
Reviewed-by: Jungseok Lee <jungseoklee85@gmail.com>
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
[will: fixed minor context changes conflicting with irq stack bits]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Function graph tracer modifies a return address (LR) in a stack frame
to hook a function's return. This will result in many useless entries
(return_to_handler) showing up in a call stack list.
We will fix this problem in a later patch ("arm64: ftrace: fix a stack
tracer's output under function graph tracer"). But since real return
addresses are saved in ret_stack[] array in struct task_struct,
unwind functions need to be notified of, in addition to a stack pointer
address, which task is being traced in order to find out real return
addresses.
This patch extends unwind functions' interfaces by adding an extra
argument of a pointer to task_struct.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Function graph tracer modifies a return address (LR) in a stack frame by
calling ftrace_prepare_return() in a traced function's function prologue.
The current code does this modification before preserving an original
address at ftrace_push_return_trace() and there is always a small window
of inconsistency when an interrupt occurs.
This doesn't matter, as far as an interrupt stack is introduced, because
stack tracer won't be invoked in an interrupt context. But it would be
better to proactively minimize such a window by moving the LR modification
after ftrace_push_return_trace().
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
sysrq_handle_reboot() re-enables interrupts while on the irq stack. The
irq_stack implementation wrongly assumed this would only ever happen
via the softirq path, allowing it to update irq_count late, in
do_softirq_own_stack().
This means if an irq occurs in sysrq_handle_reboot(), during
emergency_restart() the stack will be corrupted, as irq_count wasn't
updated.
Lose the optimisation, and instead of moving the adding/subtracting of
irq_count into irq_stack_entry/irq_stack_exit, remove it, and compare
sp_el0 (struct thread_info) with sp & ~(THREAD_SIZE - 1). This tells us
if we are on a task stack, if so, we can safely switch to the irq stack.
Finally, remove do_softirq_own_stack(), we don't need it anymore.
Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
[will: use get_thread_info macro]
Signed-off-by: Will Deacon <will.deacon@arm.com>
The arm64 MMU supports a Contiguous bit which is a hint that the TTE
is one of a set of contiguous entries which can be cached in a single
TLB entry. Supporting this bit adds new intermediate huge page sizes.
The set of huge page sizes available depends on the base page size.
Without using contiguous pages the huge page sizes are as follows.
4KB: 2MB 1GB
64KB: 512MB
With a 4KB granule, the contiguous bit groups together sets of 16 pages
and with a 64KB granule it groups sets of 32 pages. This enables two new
huge page sizes in each case, so that the full set of available sizes
is as follows.
4KB: 64KB 2MB 32MB 1GB
64KB: 2MB 512MB 16GB
If a 16KB granule is used then the contiguous bit groups 128 pages
at the PTE level and 32 pages at the PMD level.
If the base page size is set to 64KB then 2MB pages are enabled by
default. It is possible in the future to make 2MB the default huge
page size for both 4KB and 64KB granules.
Reviewed-by: Chris Metcalf <cmetcalf@ezchip.com>
Reviewed-by: Steve Capper <steve.capper@linaro.org>
Signed-off-by: David Woods <dwoods@ezchip.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The pmuserenr_el0 register value is architecturally UNKNOWN on reset.
Current kernel code resets that register value iff the core pmu device is
correctly probed in the kernel. On platforms with missing DT pmu nodes (or
disabled perf events in the kernel), the pmu is not probed, therefore the
pmuserenr_el0 register is not reset in the kernel, which means that its
value retains the reset value that is architecturally UNKNOWN (system
may run with eg pmuserenr_el0 == 0x1, which means that PMU counters access
is available at EL0, which must be disallowed).
This patch adds code that resets pmuserenr_el0 on cold boot and restores
it on core resume from shutdown, so that the pmuserenr_el0 setup is
always enforced in the kernel.
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM64.
Necessary duplication of paravirt.h and paravirt.c with ARM.
The only paravirt interface supported is pv_time_ops.steal_clock, so no
runtime pvops patching needed.
This allows us to make use of steal_account_process_tick for stolen
ticks accounting.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Back in the days where eBPF (or back then "internal BPF" ;->) was not
exposed to user space, and only the classic BPF programs internally
translated into eBPF programs, we missed the fact that for classic BPF
A and X needed to be cleared. It was fixed back then via 83d5b7ef99
("net: filter: initialize A and X registers"), and thus classic BPF
specifics were added to the eBPF interpreter core to work around it.
This added some confusion for JIT developers later on that take the
eBPF interpreter code as an example for deriving their JIT. F.e. in
f75298f5c3 ("s390/bpf: clear correct BPF accumulator register"), at
least X could leak stack memory. Furthermore, since this is only needed
for classic BPF translations and not for eBPF (verifier takes care
that read access to regs cannot be done uninitialized), more complexity
is added to JITs as they need to determine whether they deal with
migrations or native eBPF where they can just omit clearing A/X in
their prologue and thus reduce image size a bit, see f.e. cde66c2d88
("s390/bpf: Only clear A and X for converted BPF programs"). In other
cases (x86, arm64), A and X is being cleared in the prologue also for
eBPF case, which is unnecessary.
Lets move this into the BPF migration in bpf_convert_filter() where it
actually belongs as long as the number of eBPF JITs are still few. It
can thus be done generically; allowing us to remove the quirk from
__bpf_prog_run() and to slightly reduce JIT image size in case of eBPF,
while reducing code duplication on this matter in current(/future) eBPF
JITs.
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Reviewed-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
Tested-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
Cc: Zi Shen Lim <zlim.lnx@gmail.com>
Cc: Yang Shi <yang.shi@linaro.org>
Acked-by: Yang Shi <yang.shi@linaro.org>
Acked-by: Zi Shen Lim <zlim.lnx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The ARMv8.1 architecture extension allows to choose between 8-bit and
16-bit of VMID, so use this capability for KVM.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Since commit a987370 ("arm64: KVM: Fix stage-2 PGD allocation to have
per-page refcounting") there is no reference to S2_PGD_ORDER, so kill it
for the good.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The debug trapping code is pretty heavy on the "inline" attribute,
but most functions are actually referenced in the sysreg tables,
making the inlining imposible.
Removing the useless inline qualifier seems the right thing to do,
having verified that the output code is similar.
Cc: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Enable MTK_TIMER for MediaTek plaform, which will be used as
tick broadcast device and schedule clock.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
SATA clock is 815, not 915.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This enables SATA device in r8a7795-salvator-x.dts.
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds SATA device node to r8a7795.dtsi.
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
[uli: adjusted for new MSTP clock scheme]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Sigend-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add PSCI node for r8a7795 SoC, and cpu node enable-method property is
set to "psci".
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In systems with three levels of cache(PoU at L1 and PoC at L3),
PoC cache flush instructions flushes L2 and L3 caches which could affect
performance.
For cache flushes for I and D coherency, PoU should suffice.
So changing all I and D coherency related cache flushes to PoU.
Introduced a new __clean_dcache_area_pou API for dcache flush till PoU
and provided a common macro for __flush_dcache_area and
__clean_dcache_area_pou.
Also, now in __sync_icache_dcache, icache invalidation for non-aliasing
VIPT icache is done only for that particular page instead of the earlier
__flush_icache_all.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ashok Kumar <ashoks@broadcom.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
