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i40e/i40evf: AdminQ API update for new FW

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Add set_pf_context, replace set_phy_reset with set_phy_debug, add
nvm_config_read/write, remove nvm_read/write_reg_se and add some
PHY types.

With these changes we bump the API version to 1.2.

Change-ID: I4dc3aec175c2316f66fc9b726b3f7d594699d84e
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Shannon Nelson 2014-05-22 06:31:30 +00:00 • committed by Jeff Kirsher
commit f94234ee6d
3 changed files with 161 additions and 33 deletions
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90
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
View file

@ -34,7 +34,7 @@
*/ */
#define I40E_FW_API_VERSION_MAJOR 0x0001 #define I40E_FW_API_VERSION_MAJOR 0x0001
#define I40E_FW_API_VERSION_MINOR 0x0001 #define I40E_FW_API_VERSION_MINOR 0x0002
struct i40e_aq_desc { struct i40e_aq_desc {
__le16 flags; __le16 flags;
@ -123,6 +123,7 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_get_version = 0x0001, i40e_aqc_opc_get_version = 0x0001,
i40e_aqc_opc_driver_version = 0x0002, i40e_aqc_opc_driver_version = 0x0002,
i40e_aqc_opc_queue_shutdown = 0x0003, i40e_aqc_opc_queue_shutdown = 0x0003,
i40e_aqc_opc_set_pf_context = 0x0004,
/* resource ownership */ /* resource ownership */
i40e_aqc_opc_request_resource = 0x0008, i40e_aqc_opc_request_resource = 0x0008,
@ -222,13 +223,15 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_get_partner_advt = 0x0616, i40e_aqc_opc_get_partner_advt = 0x0616,
i40e_aqc_opc_set_lb_modes = 0x0618, i40e_aqc_opc_set_lb_modes = 0x0618,
i40e_aqc_opc_get_phy_wol_caps = 0x0621, i40e_aqc_opc_get_phy_wol_caps = 0x0621,
i40e_aqc_opc_set_phy_reset = 0x0622, i40e_aqc_opc_set_phy_debug = 0x0622,
i40e_aqc_opc_upload_ext_phy_fm = 0x0625, i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
/* NVM commands */ /* NVM commands */
i40e_aqc_opc_nvm_read = 0x0701, i40e_aqc_opc_nvm_read = 0x0701,
i40e_aqc_opc_nvm_erase = 0x0702, i40e_aqc_opc_nvm_erase = 0x0702,
i40e_aqc_opc_nvm_update = 0x0703, i40e_aqc_opc_nvm_update = 0x0703,
i40e_aqc_opc_nvm_config_read = 0x0704,
i40e_aqc_opc_nvm_config_write = 0x0705,
/* virtualization commands */ /* virtualization commands */
i40e_aqc_opc_send_msg_to_pf = 0x0801, i40e_aqc_opc_send_msg_to_pf = 0x0801,
@ -270,8 +273,6 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_debug_set_mode = 0xFF01, i40e_aqc_opc_debug_set_mode = 0xFF01,
i40e_aqc_opc_debug_read_reg = 0xFF03, i40e_aqc_opc_debug_read_reg = 0xFF03,
i40e_aqc_opc_debug_write_reg = 0xFF04, i40e_aqc_opc_debug_write_reg = 0xFF04,
i40e_aqc_opc_debug_read_reg_sg = 0xFF05,
i40e_aqc_opc_debug_write_reg_sg = 0xFF06,
i40e_aqc_opc_debug_modify_reg = 0xFF07, i40e_aqc_opc_debug_modify_reg = 0xFF07,
i40e_aqc_opc_debug_dump_internals = 0xFF08, i40e_aqc_opc_debug_dump_internals = 0xFF08,
i40e_aqc_opc_debug_modify_internals = 0xFF09, i40e_aqc_opc_debug_modify_internals = 0xFF09,
@ -339,6 +340,14 @@ struct i40e_aqc_queue_shutdown {
I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
/* Set PF context (0x0004, direct) */
struct i40e_aqc_set_pf_context {
u8 pf_id;
u8 reserved[15];
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
/* Request resource ownership (direct 0x0008) /* Request resource ownership (direct 0x0008)
* Release resource ownership (direct 0x0009) * Release resource ownership (direct 0x0009)
*/ */
@ -1404,11 +1413,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
struct i40e_aqc_configure_switching_comp_ets_data { struct i40e_aqc_configure_switching_comp_ets_data {
u8 reserved[4]; u8 reserved[4];
u8 tc_valid_bits; u8 tc_valid_bits;
u8 reserved1; u8 seepage;
#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
u8 tc_strict_priority_flags; u8 tc_strict_priority_flags;
u8 reserved2[17]; u8 reserved1[17];
u8 tc_bw_share_credits[8]; u8 tc_bw_share_credits[8];
u8 reserved3[96]; u8 reserved2[96];
}; };
/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
@ -1525,6 +1535,8 @@ enum i40e_aq_phy_type {
I40E_PHY_TYPE_XLPPI = 0x9, I40E_PHY_TYPE_XLPPI = 0x9,
I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
I40E_PHY_TYPE_10GBASE_AOC = 0xC,
I40E_PHY_TYPE_40GBASE_AOC = 0xD,
I40E_PHY_TYPE_100BASE_TX = 0x11, I40E_PHY_TYPE_100BASE_TX = 0x11,
I40E_PHY_TYPE_1000BASE_T = 0x12, I40E_PHY_TYPE_1000BASE_T = 0x12,
I40E_PHY_TYPE_10GBASE_T = 0x13, I40E_PHY_TYPE_10GBASE_T = 0x13,
@ -1535,7 +1547,10 @@ enum i40e_aq_phy_type {
I40E_PHY_TYPE_40GBASE_CR4 = 0x18, I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
I40E_PHY_TYPE_40GBASE_SR4 = 0x19, I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
I40E_PHY_TYPE_20GBASE_KR2 = 0x1B, I40E_PHY_TYPE_1000BASE_SX = 0x1B,
I40E_PHY_TYPE_1000BASE_LX = 0x1C,
I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
I40E_PHY_TYPE_MAX I40E_PHY_TYPE_MAX
}; };
@ -1679,6 +1694,7 @@ struct i40e_aqc_get_link_status {
#define I40E_AQ_LINK_TX_ACTIVE 0x00 #define I40E_AQ_LINK_TX_ACTIVE 0x00
#define I40E_AQ_LINK_TX_DRAINED 0x01 #define I40E_AQ_LINK_TX_DRAINED 0x01
#define I40E_AQ_LINK_TX_FLUSHED 0x03 #define I40E_AQ_LINK_TX_FLUSHED 0x03
#define I40E_AQ_LINK_FORCED_40G 0x10
u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
__le16 max_frame_size; __le16 max_frame_size;
u8 config; u8 config;
@ -1730,14 +1746,21 @@ struct i40e_aqc_set_lb_mode {
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
/* Set PHY Reset command (0x0622) */ /* Set PHY Debug command (0x0622) */
struct i40e_aqc_set_phy_reset { struct i40e_aqc_set_phy_debug {
u8 reset_flags; u8 command_flags;
#define I40E_AQ_PHY_RESET_REQUEST 0x02 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
u8 reserved[15]; u8 reserved[15];
}; };
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset); I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
enum i40e_aq_phy_reg_type { enum i40e_aq_phy_reg_type {
I40E_AQC_PHY_REG_INTERNAL = 0x1, I40E_AQC_PHY_REG_INTERNAL = 0x1,
@ -1762,6 +1785,47 @@ struct i40e_aqc_nvm_update {
I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
/* NVM Config Read (indirect 0x0704) */
struct i40e_aqc_nvm_config_read {
__le16 cmd_flags;
#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
#define ANVM_READ_SINGLE_FEATURE 0
#define ANVM_READ_MULTIPLE_FEATURES 1
__le16 element_count;
__le16 element_id; /* Feature/field ID */
u8 reserved[2];
__le32 address_high;
__le32 address_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
/* NVM Config Write (indirect 0x0705) */
struct i40e_aqc_nvm_config_write {
__le16 cmd_flags;
__le16 element_count;
u8 reserved[4];
__le32 address_high;
__le32 address_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
struct i40e_aqc_nvm_config_data_feature {
__le16 feature_id;
__le16 instance_id;
__le16 feature_options;
__le16 feature_selection;
};
struct i40e_aqc_nvm_config_data_immediate_field {
#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2
__le16 field_id;
__le16 instance_id;
__le16 field_options;
__le16 field_value;
};
/* Send to PF command (indirect 0x0801) id is only used by PF /* Send to PF command (indirect 0x0801) id is only used by PF
* Send to VF command (indirect 0x0802) id is only used by PF * Send to VF command (indirect 0x0802) id is only used by PF
* Send to Peer PF command (indirect 0x0803) * Send to Peer PF command (indirect 0x0803)

2
drivers/net/ethernet/intel/i40e/i40e_prototype.h
View file

@ -70,7 +70,7 @@ i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
u16 *fw_major_version, u16 *fw_minor_version, u16 *fw_major_version, u16 *fw_minor_version,
u16 *api_major_version, u16 *api_minor_version, u16 *api_major_version, u16 *api_minor_version,
struct i40e_asq_cmd_details *cmd_details); struct i40e_asq_cmd_details *cmd_details);
i40e_status i40e_aq_set_phy_reset(struct i40e_hw *hw, i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
struct i40e_asq_cmd_details *cmd_details); struct i40e_asq_cmd_details *cmd_details);
i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id, i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
struct i40e_asq_cmd_details *cmd_details); struct i40e_asq_cmd_details *cmd_details);

90
drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h
View file

@ -34,7 +34,7 @@
*/ */
#define I40E_FW_API_VERSION_MAJOR 0x0001 #define I40E_FW_API_VERSION_MAJOR 0x0001
#define I40E_FW_API_VERSION_MINOR 0x0001 #define I40E_FW_API_VERSION_MINOR 0x0002
#define I40E_FW_API_VERSION_A0_MINOR 0x0000 #define I40E_FW_API_VERSION_A0_MINOR 0x0000
struct i40e_aq_desc { struct i40e_aq_desc {
@ -124,6 +124,7 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_get_version = 0x0001, i40e_aqc_opc_get_version = 0x0001,
i40e_aqc_opc_driver_version = 0x0002, i40e_aqc_opc_driver_version = 0x0002,
i40e_aqc_opc_queue_shutdown = 0x0003, i40e_aqc_opc_queue_shutdown = 0x0003,
i40e_aqc_opc_set_pf_context = 0x0004,
/* resource ownership */ /* resource ownership */
i40e_aqc_opc_request_resource = 0x0008, i40e_aqc_opc_request_resource = 0x0008,
@ -223,13 +224,15 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_get_partner_advt = 0x0616, i40e_aqc_opc_get_partner_advt = 0x0616,
i40e_aqc_opc_set_lb_modes = 0x0618, i40e_aqc_opc_set_lb_modes = 0x0618,
i40e_aqc_opc_get_phy_wol_caps = 0x0621, i40e_aqc_opc_get_phy_wol_caps = 0x0621,
i40e_aqc_opc_set_phy_reset = 0x0622, i40e_aqc_opc_set_phy_debug = 0x0622,
i40e_aqc_opc_upload_ext_phy_fm = 0x0625, i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
/* NVM commands */ /* NVM commands */
i40e_aqc_opc_nvm_read = 0x0701, i40e_aqc_opc_nvm_read = 0x0701,
i40e_aqc_opc_nvm_erase = 0x0702, i40e_aqc_opc_nvm_erase = 0x0702,
i40e_aqc_opc_nvm_update = 0x0703, i40e_aqc_opc_nvm_update = 0x0703,
i40e_aqc_opc_nvm_config_read = 0x0704,
i40e_aqc_opc_nvm_config_write = 0x0705,
/* virtualization commands */ /* virtualization commands */
i40e_aqc_opc_send_msg_to_pf = 0x0801, i40e_aqc_opc_send_msg_to_pf = 0x0801,
@ -271,8 +274,6 @@ enum i40e_admin_queue_opc {
i40e_aqc_opc_debug_set_mode = 0xFF01, i40e_aqc_opc_debug_set_mode = 0xFF01,
i40e_aqc_opc_debug_read_reg = 0xFF03, i40e_aqc_opc_debug_read_reg = 0xFF03,
i40e_aqc_opc_debug_write_reg = 0xFF04, i40e_aqc_opc_debug_write_reg = 0xFF04,
i40e_aqc_opc_debug_read_reg_sg = 0xFF05,
i40e_aqc_opc_debug_write_reg_sg = 0xFF06,
i40e_aqc_opc_debug_modify_reg = 0xFF07, i40e_aqc_opc_debug_modify_reg = 0xFF07,
i40e_aqc_opc_debug_dump_internals = 0xFF08, i40e_aqc_opc_debug_dump_internals = 0xFF08,
i40e_aqc_opc_debug_modify_internals = 0xFF09, i40e_aqc_opc_debug_modify_internals = 0xFF09,
@ -340,6 +341,14 @@ struct i40e_aqc_queue_shutdown {
I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
/* Set PF context (0x0004, direct) */
struct i40e_aqc_set_pf_context {
u8 pf_id;
u8 reserved[15];
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
/* Request resource ownership (direct 0x0008) /* Request resource ownership (direct 0x0008)
* Release resource ownership (direct 0x0009) * Release resource ownership (direct 0x0009)
*/ */
@ -1408,11 +1417,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
struct i40e_aqc_configure_switching_comp_ets_data { struct i40e_aqc_configure_switching_comp_ets_data {
u8 reserved[4]; u8 reserved[4];
u8 tc_valid_bits; u8 tc_valid_bits;
u8 reserved1; u8 seepage;
#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
u8 tc_strict_priority_flags; u8 tc_strict_priority_flags;
u8 reserved2[17]; u8 reserved1[17];
u8 tc_bw_share_credits[8]; u8 tc_bw_share_credits[8];
u8 reserved3[96]; u8 reserved2[96];
}; };
/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
@ -1529,6 +1539,8 @@ enum i40e_aq_phy_type {
I40E_PHY_TYPE_XLPPI = 0x9, I40E_PHY_TYPE_XLPPI = 0x9,
I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
I40E_PHY_TYPE_10GBASE_AOC = 0xC,
I40E_PHY_TYPE_40GBASE_AOC = 0xD,
I40E_PHY_TYPE_100BASE_TX = 0x11, I40E_PHY_TYPE_100BASE_TX = 0x11,
I40E_PHY_TYPE_1000BASE_T = 0x12, I40E_PHY_TYPE_1000BASE_T = 0x12,
I40E_PHY_TYPE_10GBASE_T = 0x13, I40E_PHY_TYPE_10GBASE_T = 0x13,
@ -1539,7 +1551,10 @@ enum i40e_aq_phy_type {
I40E_PHY_TYPE_40GBASE_CR4 = 0x18, I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
I40E_PHY_TYPE_40GBASE_SR4 = 0x19, I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
I40E_PHY_TYPE_20GBASE_KR2 = 0x1B, I40E_PHY_TYPE_1000BASE_SX = 0x1B,
I40E_PHY_TYPE_1000BASE_LX = 0x1C,
I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
I40E_PHY_TYPE_MAX I40E_PHY_TYPE_MAX
}; };
@ -1683,6 +1698,7 @@ struct i40e_aqc_get_link_status {
#define I40E_AQ_LINK_TX_ACTIVE 0x00 #define I40E_AQ_LINK_TX_ACTIVE 0x00
#define I40E_AQ_LINK_TX_DRAINED 0x01 #define I40E_AQ_LINK_TX_DRAINED 0x01
#define I40E_AQ_LINK_TX_FLUSHED 0x03 #define I40E_AQ_LINK_TX_FLUSHED 0x03
#define I40E_AQ_LINK_FORCED_40G 0x10
u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
__le16 max_frame_size; __le16 max_frame_size;
u8 config; u8 config;
@ -1734,14 +1750,21 @@ struct i40e_aqc_set_lb_mode {
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
/* Set PHY Reset command (0x0622) */ /* Set PHY Debug command (0x0622) */
struct i40e_aqc_set_phy_reset { struct i40e_aqc_set_phy_debug {
u8 reset_flags; u8 command_flags;
#define I40E_AQ_PHY_RESET_REQUEST 0x02 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
u8 reserved[15]; u8 reserved[15];
}; };
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset); I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
enum i40e_aq_phy_reg_type { enum i40e_aq_phy_reg_type {
I40E_AQC_PHY_REG_INTERNAL = 0x1, I40E_AQC_PHY_REG_INTERNAL = 0x1,
@ -1766,6 +1789,47 @@ struct i40e_aqc_nvm_update {
I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
/* NVM Config Read (indirect 0x0704) */
struct i40e_aqc_nvm_config_read {
__le16 cmd_flags;
#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
#define ANVM_READ_SINGLE_FEATURE 0
#define ANVM_READ_MULTIPLE_FEATURES 1
__le16 element_count;
__le16 element_id; /* Feature/field ID */
u8 reserved[2];
__le32 address_high;
__le32 address_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
/* NVM Config Write (indirect 0x0705) */
struct i40e_aqc_nvm_config_write {
__le16 cmd_flags;
__le16 element_count;
u8 reserved[4];
__le32 address_high;
__le32 address_low;
};
I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
struct i40e_aqc_nvm_config_data_feature {
__le16 feature_id;
__le16 instance_id;
__le16 feature_options;
__le16 feature_selection;
};
struct i40e_aqc_nvm_config_data_immediate_field {
#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2
__le16 field_id;
__le16 instance_id;
__le16 field_options;
__le16 field_value;
};
/* Send to PF command (indirect 0x0801) id is only used by PF /* Send to PF command (indirect 0x0801) id is only used by PF
* Send to VF command (indirect 0x0802) id is only used by PF * Send to VF command (indirect 0x0802) id is only used by PF
* Send to Peer PF command (indirect 0x0803) * Send to Peer PF command (indirect 0x0803)