Merge commit 'v2.6.29-rc4' into sched/core
This commit is contained in:
commit
f437e8b53e
322 changed files with 5581 additions and 3850 deletions
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@ -14,6 +14,7 @@
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#define ACPI_PDC_SMP_T_SWCOORD (0x0080)
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#define ACPI_PDC_C_C1_FFH (0x0100)
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#define ACPI_PDC_C_C2C3_FFH (0x0200)
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#define ACPI_PDC_SMP_P_HWCOORD (0x0800)
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#define ACPI_PDC_EST_CAPABILITY_SMP (ACPI_PDC_SMP_C1PT | \
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ACPI_PDC_C_C1_HALT | \
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@ -22,6 +23,7 @@
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#define ACPI_PDC_EST_CAPABILITY_SWSMP (ACPI_PDC_SMP_C1PT | \
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ACPI_PDC_C_C1_HALT | \
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ACPI_PDC_SMP_P_SWCOORD | \
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ACPI_PDC_SMP_P_HWCOORD | \
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ACPI_PDC_P_FFH)
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#define ACPI_PDC_C_CAPABILITY_SMP (ACPI_PDC_SMP_C2C3 | \
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@ -90,7 +90,6 @@ header-y += if_ppp.h
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header-y += if_slip.h
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header-y += if_strip.h
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header-y += if_tun.h
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header-y += if_tunnel.h
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header-y += in_route.h
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header-y += ioctl.h
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header-y += ip6_tunnel.h
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@ -236,6 +235,7 @@ unifdef-y += if_phonet.h
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unifdef-y += if_pppol2tp.h
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unifdef-y += if_pppox.h
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unifdef-y += if_tr.h
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unifdef-y += if_tunnel.h
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unifdef-y += if_vlan.h
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unifdef-y += igmp.h
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unifdef-y += inet_diag.h
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@ -17,9 +17,11 @@ typedef u64 async_cookie_t;
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typedef void (async_func_ptr) (void *data, async_cookie_t cookie);
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extern async_cookie_t async_schedule(async_func_ptr *ptr, void *data);
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extern async_cookie_t async_schedule_special(async_func_ptr *ptr, void *data, struct list_head *list);
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extern async_cookie_t async_schedule_domain(async_func_ptr *ptr, void *data,
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struct list_head *list);
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extern void async_synchronize_full(void);
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extern void async_synchronize_full_special(struct list_head *list);
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extern void async_synchronize_full_domain(struct list_head *list);
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extern void async_synchronize_cookie(async_cookie_t cookie);
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extern void async_synchronize_cookie_special(async_cookie_t cookie, struct list_head *list);
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extern void async_synchronize_cookie_domain(async_cookie_t cookie,
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struct list_head *list);
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@ -731,12 +731,17 @@ static inline int ata_id_current_chs_valid(const u16 *id)
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static inline int ata_id_is_cfa(const u16 *id)
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{
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if (id[ATA_ID_CONFIG] == 0x848A) /* Standard CF */
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if (id[ATA_ID_CONFIG] == 0x848A) /* Traditional CF */
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return 1;
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/* Could be CF hiding as standard ATA */
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if (ata_id_major_version(id) >= 3 &&
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id[ATA_ID_COMMAND_SET_1] != 0xFFFF &&
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(id[ATA_ID_COMMAND_SET_1] & (1 << 2)))
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/*
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* CF specs don't require specific value in the word 0 anymore and yet
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* they forbid to report the ATA version in the word 80 and require the
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* CFA feature set support to be indicated in the word 83 in this case.
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* Unfortunately, some cards only follow either of this requirements,
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* and while those that don't indicate CFA feature support need some
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* sort of quirk list, it seems impractical for the ones that do...
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*/
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if ((id[ATA_ID_COMMAND_SET_2] & 0xC004) == 0x4004)
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return 1;
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return 0;
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}
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@ -960,6 +960,21 @@ extern struct fb_info *registered_fb[FB_MAX];
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extern int num_registered_fb;
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extern struct class *fb_class;
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static inline int lock_fb_info(struct fb_info *info)
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{
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mutex_lock(&info->lock);
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if (!info->fbops) {
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mutex_unlock(&info->lock);
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return 0;
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}
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return 1;
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}
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static inline void unlock_fb_info(struct fb_info *info)
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{
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mutex_unlock(&info->lock);
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}
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static inline void __fb_pad_aligned_buffer(u8 *dst, u32 d_pitch,
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u8 *src, u32 s_pitch, u32 height)
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{
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@ -2,7 +2,10 @@
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#define _IF_TUNNEL_H_
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#include <linux/types.h>
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#ifdef __KERNEL__
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#include <linux/ip.h>
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#endif
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#define SIOCGETTUNNEL (SIOCDEVPRIVATE + 0)
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#define SIOCADDTUNNEL (SIOCDEVPRIVATE + 1)
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@ -480,7 +480,8 @@ static inline char *pack_hex_byte(char *buf, u8 byte)
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/*
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* swap - swap value of @a and @b
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*/
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#define swap(a, b) ({ typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; })
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#define swap(a, b) \
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do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
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/**
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* container_of - cast a member of a structure out to the containing structure
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@ -380,6 +380,7 @@ enum {
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ATA_HORKAGE_ATAPI_MOD16_DMA = (1 << 11), /* use ATAPI DMA for commands
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not multiple of 16 bytes */
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ATA_HORKAGE_FIRMWARE_WARN = (1 << 12), /* firwmare update warning */
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ATA_HORKAGE_1_5_GBPS = (1 << 13), /* force 1.5 Gbps */
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/* DMA mask for user DMA control: User visible values; DO NOT
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renumber */
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@ -580,7 +581,7 @@ struct ata_device {
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acpi_handle acpi_handle;
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union acpi_object *gtf_cache;
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#endif
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/* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */
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/* n_sector is CLEAR_BEGIN, read comment above CLEAR_BEGIN */
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u64 n_sectors; /* size of device, if ATA */
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unsigned int class; /* ATA_DEV_xxx */
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unsigned long unpark_deadline;
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@ -605,20 +606,22 @@ struct ata_device {
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u16 heads; /* Number of heads */
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u16 sectors; /* Number of sectors per track */
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/* error history */
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int spdn_cnt;
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struct ata_ering ering;
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union {
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u16 id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */
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u32 gscr[SATA_PMP_GSCR_DWORDS]; /* PMP GSCR block */
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};
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/* error history */
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int spdn_cnt;
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/* ering is CLEAR_END, read comment above CLEAR_END */
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struct ata_ering ering;
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};
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/* Offset into struct ata_device. Fields above it are maintained
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* acress device init. Fields below are zeroed.
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/* Fields between ATA_DEVICE_CLEAR_BEGIN and ATA_DEVICE_CLEAR_END are
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* cleared to zero on ata_dev_init().
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*/
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#define ATA_DEVICE_CLEAR_OFFSET offsetof(struct ata_device, n_sectors)
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#define ATA_DEVICE_CLEAR_BEGIN offsetof(struct ata_device, n_sectors)
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#define ATA_DEVICE_CLEAR_END offsetof(struct ata_device, ering)
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struct ata_eh_info {
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struct ata_device *dev; /* offending device */
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@ -407,7 +407,6 @@ static inline local_t *__module_ref_addr(struct module *mod, int cpu)
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static inline void __module_get(struct module *module)
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{
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if (module) {
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BUG_ON(module_refcount(module) == 0);
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local_inc(__module_ref_addr(module, get_cpu()));
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put_cpu();
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}
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@ -684,7 +684,7 @@ int pci_enable_rom(struct pci_dev *pdev);
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void pci_disable_rom(struct pci_dev *pdev);
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void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
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void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
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size_t pci_get_rom_size(void __iomem *rom, size_t size);
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size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
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/* Power management related routines */
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int pci_save_state(struct pci_dev *dev);
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@ -132,6 +132,8 @@ static inline void __remove_wait_queue(wait_queue_head_t *head,
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list_del(&old->task_list);
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}
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void __wake_up_common(wait_queue_head_t *q, unsigned int mode,
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int nr_exclusive, int sync, void *key);
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void __wake_up(wait_queue_head_t *q, unsigned int mode, int nr, void *key);
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extern void __wake_up_locked(wait_queue_head_t *q, unsigned int mode);
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extern void __wake_up_sync(wait_queue_head_t *q, unsigned int mode, int nr);
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@ -333,16 +335,19 @@ do { \
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for (;;) { \
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prepare_to_wait_exclusive(&wq, &__wait, \
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TASK_INTERRUPTIBLE); \
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if (condition) \
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if (condition) { \
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finish_wait(&wq, &__wait); \
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break; \
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} \
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if (!signal_pending(current)) { \
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schedule(); \
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continue; \
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} \
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ret = -ERESTARTSYS; \
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abort_exclusive_wait(&wq, &__wait, \
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TASK_INTERRUPTIBLE, NULL); \
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break; \
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} \
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finish_wait(&wq, &__wait); \
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} while (0)
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#define wait_event_interruptible_exclusive(wq, condition) \
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@ -431,6 +436,8 @@ extern long interruptible_sleep_on_timeout(wait_queue_head_t *q,
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void prepare_to_wait(wait_queue_head_t *q, wait_queue_t *wait, int state);
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void prepare_to_wait_exclusive(wait_queue_head_t *q, wait_queue_t *wait, int state);
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void finish_wait(wait_queue_head_t *q, wait_queue_t *wait);
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void abort_exclusive_wait(wait_queue_head_t *q, wait_queue_t *wait,
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unsigned int mode, void *key);
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int autoremove_wake_function(wait_queue_t *wait, unsigned mode, int sync, void *key);
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int wake_bit_function(wait_queue_t *wait, unsigned mode, int sync, void *key);
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@ -21,9 +21,9 @@
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#define I2C_CNTL_1 0x0094
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#define PALETTE_INDEX 0x00b0
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#define PALETTE_DATA 0x00b4
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#define CONFIG_CNTL 0x00e0
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#define CNFG_CNTL 0x00e0
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#define GEN_RESET_CNTL 0x00f0
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#define CONFIG_MEMSIZE 0x00f8
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#define CNFG_MEMSIZE 0x00f8
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#define MEM_CNTL 0x0140
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#define MEM_POWER_MISC 0x015c
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#define AGP_BASE 0x0170
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@ -103,7 +103,7 @@
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#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
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#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
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#define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
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#define CNFG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
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/* General I/O Control */
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#define GP_IO 0x0078 /* Dword offset 0_1E */
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@ -146,8 +146,8 @@
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#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */
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/* Configuration */
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#define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */
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#define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */
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#define CNFG_STAT1 0x0094 /* Dword offset 0_25 */
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#define CNFG_STAT2 0x0098 /* Dword offset 0_26 */
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/* Bus Control */
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#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */
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@ -190,9 +190,9 @@
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#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */
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/* Configuration */
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#define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
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#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
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#define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */
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#define CNFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
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#define CNFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
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#define CNFG_STAT0 0x00E4 /* Dword offset 0_39 */
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/* Test and Debug */
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#define CRC_SIG 0x00E8 /* Dword offset 0_3A */
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@ -851,17 +851,17 @@
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#define PLL_YCLK_CNTL 0x29
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#define PM_DYN_CLK_CNTL 0x2A
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/* CONFIG_CNTL register constants */
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/* CNFG_CNTL register constants */
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#define APERTURE_4M_ENABLE 1
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#define APERTURE_8M_ENABLE 2
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#define VGA_APERTURE_ENABLE 4
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/* CONFIG_STAT0 register constants (GX, CX) */
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/* CNFG_STAT0 register constants (GX, CX) */
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#define CFG_BUS_TYPE 0x00000007
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#define CFG_MEM_TYPE 0x00000038
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#define CFG_INIT_DAC_TYPE 0x00000e00
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/* CONFIG_STAT0 register constants (CT, ET, VT) */
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/* CNFG_STAT0 register constants (CT, ET, VT) */
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#define CFG_MEM_TYPE_xT 0x00000007
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#define ISA 0
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@ -942,7 +942,7 @@
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#define PCI_ATI_VENDOR_ID 0x1002
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/* CONFIG_CHIP_ID register constants */
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/* CNFG_CHIP_ID register constants */
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#define CFG_CHIP_TYPE 0x0000FFFF
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#define CFG_CHIP_CLASS 0x00FF0000
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#define CFG_CHIP_REV 0xFF000000
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@ -951,7 +951,7 @@
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#define CFG_CHIP_MINOR 0xC0000000
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/* Chip IDs read from CONFIG_CHIP_ID */
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/* Chip IDs read from CNFG_CHIP_ID */
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/* mach64GX family */
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#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */
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@ -1254,7 +1254,7 @@
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#define CRTC2_DISPLAY_DIS 0x00000400
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/* LCD register indices */
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#define CONFIG_PANEL 0x00
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#define CNFG_PANEL 0x00
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#define LCD_GEN_CNTL 0x01
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#define DSTN_CONTROL 0x02
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#define HFB_PITCH_ADDR 0x03
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@ -11,13 +11,13 @@
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#define HI_STAT 0x004C
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#define BUS_CNTL1 0x0034
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#define I2C_CNTL_1 0x0094
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#define CONFIG_CNTL 0x00E0
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#define CONFIG_MEMSIZE 0x00F8
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#define CONFIG_APER_0_BASE 0x0100
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#define CONFIG_APER_1_BASE 0x0104
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#define CONFIG_APER_SIZE 0x0108
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#define CONFIG_REG_1_BASE 0x010C
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#define CONFIG_REG_APER_SIZE 0x0110
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#define CNFG_CNTL 0x00E0
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#define CNFG_MEMSIZE 0x00F8
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#define CNFG_APER_0_BASE 0x0100
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#define CNFG_APER_1_BASE 0x0104
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#define CNFG_APER_SIZE 0x0108
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#define CNFG_REG_1_BASE 0x010C
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#define CNFG_REG_APER_SIZE 0x0110
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#define PAD_AGPINPUT_DELAY 0x0164
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#define PAD_CTLR_STRENGTH 0x0168
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#define PAD_CTLR_UPDATE 0x016C
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@ -509,7 +509,7 @@
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/* CLOCK_CNTL_INDEX bit constants */
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#define PLL_WR_EN 0x00000080
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/* CONFIG_CNTL bit constants */
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/* CNFG_CNTL bit constants */
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#define CFG_VGA_RAM_EN 0x00000100
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#define CFG_ATI_REV_ID_MASK (0xf << 16)
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#define CFG_ATI_REV_A11 (0 << 16)
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@ -980,7 +980,7 @@
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/* masks */
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#define CONFIG_MEMSIZE_MASK 0x1f000000
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#define CNFG_MEMSIZE_MASK 0x1f000000
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#define MEM_CFG_TYPE 0x40000000
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#define DST_OFFSET_MASK 0x003fffff
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#define DST_PITCH_MASK 0x3fc00000
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