mfd: rtsx: Configure to enter a deeper power-saving mode in S3
Set a bit to enable rts5227 and rts5249 to enter a deeper internal power-saving mode in S3, and recover it after resuming. Signed-off-by: Wei WANG <wei_wang@realsil.com.cn> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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					 7 changed files with 15 additions and 7 deletions
				
			
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			@ -86,7 +86,7 @@ static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr)
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		map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg));
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}
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static void rtl8411_force_power_down(struct rtsx_pcr *pcr)
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static void rtl8411_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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	rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
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}
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			@ -59,7 +59,7 @@ static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
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	}
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}
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static void rts5209_force_power_down(struct rtsx_pcr *pcr)
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static void rts5209_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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	rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
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}
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			@ -83,13 +83,16 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
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		pcr->flags |= PCR_REVERSE_SOCKET;
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}
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static void rts5227_force_power_down(struct rtsx_pcr *pcr)
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static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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	/* Set relink_time to 0 */
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	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
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	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
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	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
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	if (pm_state == HOST_ENTER_S3)
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		rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
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	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
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}
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			@ -123,6 +126,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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	else
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		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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				AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88);
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	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
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	return rtsx_pci_send_cmd(pcr, 100);
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}
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			@ -56,7 +56,7 @@ static void rts5229_fetch_vendor_settings(struct rtsx_pcr *pcr)
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		map_sd_drive(rtsx_reg_to_sd30_drive_sel_3v3(reg));
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}
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static void rts5229_force_power_down(struct rtsx_pcr *pcr)
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static void rts5229_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
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}
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			@ -88,13 +88,16 @@ static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
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		pcr->flags |= PCR_REVERSE_SOCKET;
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}
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static void rts5249_force_power_down(struct rtsx_pcr *pcr)
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static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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	/* Set relink_time to 0 */
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	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
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	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
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	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
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	if (pm_state == HOST_ENTER_S3)
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		rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
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	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
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}
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			@ -119,6 +122,7 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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	else
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		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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				AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
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	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
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	return rtsx_pci_send_cmd(pcr, 100);
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}
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			@ -939,7 +939,7 @@ static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
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	rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
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	if (pcr->ops->force_power_down)
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		pcr->ops->force_power_down(pcr);
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		pcr->ops->force_power_down(pcr, pm_state);
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}
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static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
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			@ -779,7 +779,7 @@ struct pcr_ops {
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	unsigned int	(*cd_deglitch)(struct rtsx_pcr *pcr);
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	int		(*conv_clk_and_div_n)(int clk, int dir);
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	void		(*fetch_vendor_settings)(struct rtsx_pcr *pcr);
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	void		(*force_power_down)(struct rtsx_pcr *pcr);
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	void		(*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
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};
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enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};
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