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Merge branch 'master' into for-next

Browse source 
Merge with latest Linus' tree, as I have incoming patches
that fix code that is newer than current HEAD of for-next.

Conflicts:
	drivers/net/ethernet/realtek/r8169.c
This commit is contained in:
Jiri Kosina 2012-04-08 21:48:52 +02:00
commit e75d660672
10951 changed files with 514814 additions and 339524 deletions
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23
include/linux/mfd/88pm860x.h
View file

@ -263,6 +263,22 @@ enum {
#define PM8607_PD_PREBIAS_MASK (0x1F << 0)
#define PM8607_PD_PRECHG_MASK (7 << 5)
#define PM8606_REF_GP_OSC_OFF 0
#define PM8606_REF_GP_OSC_ON 1
#define PM8606_REF_GP_OSC_UNKNOWN 2
/* Clients of reference group and 8MHz oscillator in 88PM8606 */
enum pm8606_ref_gp_and_osc_clients {
REF_GP_NO_CLIENTS = 0,
WLED1_DUTY = (1<<0), /*PF 0x02.7:0*/
WLED2_DUTY = (1<<1), /*PF 0x04.7:0*/
WLED3_DUTY = (1<<2), /*PF 0x06.7:0*/
RGB1_ENABLE = (1<<3), /*PF 0x07.1*/
RGB2_ENABLE = (1<<4), /*PF 0x07.2*/
LDO_VBR_EN = (1<<5), /*PF 0x12.0*/
REF_GP_MAX_CLIENT = 0xFFFF
};
/* Interrupt Number in 88PM8607 */
enum {
PM8607_IRQ_ONKEY,
@ -298,6 +314,7 @@ enum {
struct pm860x_chip {
struct device *dev;
struct mutex irq_lock;
struct mutex osc_lock;
struct i2c_client *client;
struct i2c_client *companion; /* companion chip client */
struct regmap *regmap;
@ -305,12 +322,15 @@ struct pm860x_chip {
int buck3_double; /* DVC ramp slope double */
unsigned short companion_addr;
unsigned short osc_vote;
int id;
int irq_mode;
int irq_base;
int core_irq;
unsigned char chip_version;
unsigned char osc_status;
unsigned int wakeup_flag;
};
enum {
@ -369,6 +389,9 @@ struct pm860x_platform_data {
int num_regulators;
};
extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short);
extern int pm8606_osc_disable(struct pm860x_chip *, unsigned short);
extern int pm860x_reg_read(struct i2c_client *, int);
extern int pm860x_reg_write(struct i2c_client *, int, unsigned char);
extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *);

283
include/linux/mfd/abx500.h
View file

@ -14,9 +14,10 @@
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
#include <linux/device.h>
#include <linux/regulator/machine.h>
struct device;
#ifndef MFD_ABX500_H
#define MFD_ABX500_H
@ -33,13 +34,6 @@
#define AB5500_1_1 0x21
#define AB5500_2_0 0x24
/* AB8500 CIDs*/
#define AB8500_CUT1P0 0x10
#define AB8500_CUT1P1 0x11
#define AB8500_CUT2P0 0x20
#define AB8500_CUT3P0 0x30
#define AB8500_CUT3P3 0x33
/*
* AB3100, EVENTA1, A2 and A3 event register flags
* these are catenated into a single 32-bit flag in the code
@ -152,6 +146,279 @@ struct abx500_init_settings {
u8 setting;
};
/* Battery driver related data */
/*
* ADC for the battery thermistor.
* When using the ABx500_ADC_THERM_BATCTRL the battery ID resistor is combined
* with a NTC resistor to both identify the battery and to measure its
* temperature. Different phone manufactures uses different techniques to both
* identify the battery and to read its temperature.
*/
enum abx500_adc_therm {
ABx500_ADC_THERM_BATCTRL,
ABx500_ADC_THERM_BATTEMP,
};
/**
* struct abx500_res_to_temp - defines one point in a temp to res curve. To
* be used in battery packs that combines the identification resistor with a
* NTC resistor.
* @temp: battery pack temperature in Celcius
* @resist: NTC resistor net total resistance
*/
struct abx500_res_to_temp {
int temp;
int resist;
};
/**
* struct abx500_v_to_cap - Table for translating voltage to capacity
* @voltage: Voltage in mV
* @capacity: Capacity in percent
*/
struct abx500_v_to_cap {
int voltage;
int capacity;
};
/* Forward declaration */
struct abx500_fg;
/**
* struct abx500_fg_parameters - Fuel gauge algorithm parameters, in seconds
* if not specified
* @recovery_sleep_timer: Time between measurements while recovering
* @recovery_total_time: Total recovery time
* @init_timer: Measurement interval during startup
* @init_discard_time: Time we discard voltage measurement at startup
* @init_total_time: Total init time during startup
* @high_curr_time: Time current has to be high to go to recovery
* @accu_charging: FG accumulation time while charging
* @accu_high_curr: FG accumulation time in high current mode
* @high_curr_threshold: High current threshold, in mA
* @lowbat_threshold: Low battery threshold, in mV
* @overbat_threshold: Over battery threshold, in mV
* @battok_falling_th_sel0 Threshold in mV for battOk signal sel0
* Resolution in 50 mV step.
* @battok_raising_th_sel1 Threshold in mV for battOk signal sel1
* Resolution in 50 mV step.
* @user_cap_limit Capacity reported from user must be within this
* limit to be considered as sane, in percentage
* points.
* @maint_thres This is the threshold where we stop reporting
* battery full while in maintenance, in per cent
*/
struct abx500_fg_parameters {
int recovery_sleep_timer;
int recovery_total_time;
int init_timer;
int init_discard_time;
int init_total_time;
int high_curr_time;
int accu_charging;
int accu_high_curr;
int high_curr_threshold;
int lowbat_threshold;
int overbat_threshold;
int battok_falling_th_sel0;
int battok_raising_th_sel1;
int user_cap_limit;
int maint_thres;
};
/**
* struct abx500_charger_maximization - struct used by the board config.
* @use_maxi: Enable maximization for this battery type
* @maxi_chg_curr: Maximum charger current allowed
* @maxi_wait_cycles: cycles to wait before setting charger current
* @charger_curr_step delta between two charger current settings (mA)
*/
struct abx500_maxim_parameters {
bool ena_maxi;
int chg_curr;
int wait_cycles;
int charger_curr_step;
};
/**
* struct abx500_battery_type - different batteries supported
* @name: battery technology
* @resis_high: battery upper resistance limit
* @resis_low: battery lower resistance limit
* @charge_full_design: Maximum battery capacity in mAh
* @nominal_voltage: Nominal voltage of the battery in mV
* @termination_vol: max voltage upto which battery can be charged
* @termination_curr battery charging termination current in mA
* @recharge_vol battery voltage limit that will trigger a new
* full charging cycle in the case where maintenan-
* -ce charging has been disabled
* @normal_cur_lvl: charger current in normal state in mA
* @normal_vol_lvl: charger voltage in normal state in mV
* @maint_a_cur_lvl: charger current in maintenance A state in mA
* @maint_a_vol_lvl: charger voltage in maintenance A state in mV
* @maint_a_chg_timer_h: charge time in maintenance A state
* @maint_b_cur_lvl: charger current in maintenance B state in mA
* @maint_b_vol_lvl: charger voltage in maintenance B state in mV
* @maint_b_chg_timer_h: charge time in maintenance B state
* @low_high_cur_lvl: charger current in temp low/high state in mA
* @low_high_vol_lvl: charger voltage in temp low/high state in mV'
* @battery_resistance: battery inner resistance in mOhm.
* @n_r_t_tbl_elements: number of elements in r_to_t_tbl
* @r_to_t_tbl: table containing resistance to temp points
* @n_v_cap_tbl_elements: number of elements in v_to_cap_tbl
* @v_to_cap_tbl: Voltage to capacity (in %) table
* @n_batres_tbl_elements number of elements in the batres_tbl
* @batres_tbl battery internal resistance vs temperature table
*/
struct abx500_battery_type {
int name;
int resis_high;
int resis_low;
int charge_full_design;
int nominal_voltage;
int termination_vol;
int termination_curr;
int recharge_vol;
int normal_cur_lvl;
int normal_vol_lvl;
int maint_a_cur_lvl;
int maint_a_vol_lvl;
int maint_a_chg_timer_h;
int maint_b_cur_lvl;
int maint_b_vol_lvl;
int maint_b_chg_timer_h;
int low_high_cur_lvl;
int low_high_vol_lvl;
int battery_resistance;
int n_temp_tbl_elements;
struct abx500_res_to_temp *r_to_t_tbl;
int n_v_cap_tbl_elements;
struct abx500_v_to_cap *v_to_cap_tbl;
int n_batres_tbl_elements;
struct batres_vs_temp *batres_tbl;
};
/**
* struct abx500_bm_capacity_levels - abx500 capacity level data
* @critical: critical capacity level in percent
* @low: low capacity level in percent
* @normal: normal capacity level in percent
* @high: high capacity level in percent
* @full: full capacity level in percent
*/
struct abx500_bm_capacity_levels {
int critical;
int low;
int normal;
int high;
int full;
};
/**
* struct abx500_bm_charger_parameters - Charger specific parameters
* @usb_volt_max: maximum allowed USB charger voltage in mV
* @usb_curr_max: maximum allowed USB charger current in mA
* @ac_volt_max: maximum allowed AC charger voltage in mV
* @ac_curr_max: maximum allowed AC charger current in mA
*/
struct abx500_bm_charger_parameters {
int usb_volt_max;
int usb_curr_max;
int ac_volt_max;
int ac_curr_max;
};
/**
* struct abx500_bm_data - abx500 battery management data
* @temp_under under this temp, charging is stopped
* @temp_low between this temp and temp_under charging is reduced
* @temp_high between this temp and temp_over charging is reduced
* @temp_over over this temp, charging is stopped
* @temp_now present battery temperature
* @temp_interval_chg temperature measurement interval in s when charging
* @temp_interval_nochg temperature measurement interval in s when not charging
* @main_safety_tmr_h safety timer for main charger
* @usb_safety_tmr_h safety timer for usb charger
* @bkup_bat_v voltage which we charge the backup battery with
* @bkup_bat_i current which we charge the backup battery with
* @no_maintenance indicates that maintenance charging is disabled
* @abx500_adc_therm placement of thermistor, batctrl or battemp adc
* @chg_unknown_bat flag to enable charging of unknown batteries
* @enable_overshoot flag to enable VBAT overshoot control
* @auto_trig flag to enable auto adc trigger
* @fg_res resistance of FG resistor in 0.1mOhm
* @n_btypes number of elements in array bat_type
* @batt_id index of the identified battery in array bat_type
* @interval_charging charge alg cycle period time when charging (sec)
* @interval_not_charging charge alg cycle period time when not charging (sec)
* @temp_hysteresis temperature hysteresis
* @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
* @maxi: maximization parameters
* @cap_levels capacity in percent for the different capacity levels
* @bat_type table of supported battery types
* @chg_params charger parameters
* @fg_params fuel gauge parameters
*/
struct abx500_bm_data {
int temp_under;
int temp_low;
int temp_high;
int temp_over;
int temp_now;
int temp_interval_chg;
int temp_interval_nochg;
int main_safety_tmr_h;
int usb_safety_tmr_h;
int bkup_bat_v;
int bkup_bat_i;
bool no_maintenance;
bool chg_unknown_bat;
bool enable_overshoot;
bool auto_trig;
enum abx500_adc_therm adc_therm;
int fg_res;
int n_btypes;
int batt_id;
int interval_charging;
int interval_not_charging;
int temp_hysteresis;
int gnd_lift_resistance;
const struct abx500_maxim_parameters *maxi;
const struct abx500_bm_capacity_levels *cap_levels;
const struct abx500_battery_type *bat_type;
const struct abx500_bm_charger_parameters *chg_params;
const struct abx500_fg_parameters *fg_params;
};
struct abx500_chargalg_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct abx500_charger_platform_data {
char **supplied_to;
size_t num_supplicants;
bool autopower_cfg;
};
struct abx500_btemp_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct abx500_fg_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct abx500_bm_plat_data {
struct abx500_bm_data *battery;
struct abx500_charger_platform_data *charger;
struct abx500_btemp_platform_data *btemp;
struct abx500_fg_platform_data *fg;
struct abx500_chargalg_platform_data *chargalg;
};
int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 value);
int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,

2
include/linux/mfd/abx500/ab5500.h
View file

@ -6,7 +6,7 @@
#ifndef MFD_AB5500_H
#define MFD_AB5500_H
#include <linux/device.h>
struct device;
enum ab5500_devid {
AB5500_DEVID_ADC,

474
include/linux/mfd/abx500/ab8500-bm.h Normal file
View file

@ -0,0 +1,474 @@
/*
* Copyright ST-Ericsson 2012.
*
* Author: Arun Murthy <arun.murthy@stericsson.com>
* Licensed under GPLv2.
*/
#ifndef _AB8500_BM_H
#define _AB8500_BM_H
#include <linux/kernel.h>
#include <linux/mfd/abx500.h>
/*
* System control 2 register offsets.
* bank = 0x02
*/
#define AB8500_MAIN_WDOG_CTRL_REG 0x01
#define AB8500_LOW_BAT_REG 0x03
#define AB8500_BATT_OK_REG 0x04
/*
* USB/ULPI register offsets
* Bank : 0x5
*/
#define AB8500_USB_LINE_STAT_REG 0x80
/*
* Charger / status register offfsets
* Bank : 0x0B
*/
#define AB8500_CH_STATUS1_REG 0x00
#define AB8500_CH_STATUS2_REG 0x01
#define AB8500_CH_USBCH_STAT1_REG 0x02
#define AB8500_CH_USBCH_STAT2_REG 0x03
#define AB8500_CH_FSM_STAT_REG 0x04
#define AB8500_CH_STAT_REG 0x05
/*
* Charger / control register offfsets
* Bank : 0x0B
*/
#define AB8500_CH_VOLT_LVL_REG 0x40
#define AB8500_CH_VOLT_LVL_MAX_REG 0x41 /*Only in Cut2.0*/
#define AB8500_CH_OPT_CRNTLVL_REG 0x42
#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x43 /*Only in Cut2.0*/
#define AB8500_CH_WD_TIMER_REG 0x50
#define AB8500_CHARG_WD_CTRL 0x51
#define AB8500_BTEMP_HIGH_TH 0x52
#define AB8500_LED_INDICATOR_PWM_CTRL 0x53
#define AB8500_LED_INDICATOR_PWM_DUTY 0x54
#define AB8500_BATT_OVV 0x55
#define AB8500_CHARGER_CTRL 0x56
#define AB8500_BAT_CTRL_CURRENT_SOURCE 0x60 /*Only in Cut2.0*/
/*
* Charger / main control register offsets
* Bank : 0x0B
*/
#define AB8500_MCH_CTRL1 0x80
#define AB8500_MCH_CTRL2 0x81
#define AB8500_MCH_IPT_CURLVL_REG 0x82
#define AB8500_CH_WD_REG 0x83
/*
* Charger / USB control register offsets
* Bank : 0x0B
*/
#define AB8500_USBCH_CTRL1_REG 0xC0
#define AB8500_USBCH_CTRL2_REG 0xC1
#define AB8500_USBCH_IPT_CRNTLVL_REG 0xC2
/*
* Gas Gauge register offsets
* Bank : 0x0C
*/
#define AB8500_GASG_CC_CTRL_REG 0x00
#define AB8500_GASG_CC_ACCU1_REG 0x01
#define AB8500_GASG_CC_ACCU2_REG 0x02
#define AB8500_GASG_CC_ACCU3_REG 0x03
#define AB8500_GASG_CC_ACCU4_REG 0x04
#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x05
#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x06
#define AB8500_GASG_CC_SMPL_CNVL_REG 0x07
#define AB8500_GASG_CC_SMPL_CNVH_REG 0x08
#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x09
#define AB8500_GASG_CC_OFFSET_REG 0x0A
#define AB8500_GASG_CC_NCOV_ACCU 0x10
#define AB8500_GASG_CC_NCOV_ACCU_CTRL 0x11
#define AB8500_GASG_CC_NCOV_ACCU_LOW 0x12
#define AB8500_GASG_CC_NCOV_ACCU_MED 0x13
#define AB8500_GASG_CC_NCOV_ACCU_HIGH 0x14
/*
* Interrupt register offsets
* Bank : 0x0E
*/
#define AB8500_IT_SOURCE2_REG 0x01
#define AB8500_IT_SOURCE21_REG 0x14
/*
* RTC register offsets
* Bank: 0x0F
*/
#define AB8500_RTC_BACKUP_CHG_REG 0x0C
#define AB8500_RTC_CC_CONF_REG 0x01
#define AB8500_RTC_CTRL_REG 0x0B
/*
* OTP register offsets
* Bank : 0x15
*/
#define AB8500_OTP_CONF_15 0x0E
/* GPADC constants from AB8500 spec, UM0836 */
#define ADC_RESOLUTION 1024
#define ADC_CH_MAIN_MIN 0
#define ADC_CH_MAIN_MAX 20030
#define ADC_CH_VBUS_MIN 0
#define ADC_CH_VBUS_MAX 20030
#define ADC_CH_VBAT_MIN 2300
#define ADC_CH_VBAT_MAX 4800
#define ADC_CH_BKBAT_MIN 0
#define ADC_CH_BKBAT_MAX 3200
/* Main charge i/p current */
#define MAIN_CH_IP_CUR_0P9A 0x80
#define MAIN_CH_IP_CUR_1P0A 0x90
#define MAIN_CH_IP_CUR_1P1A 0xA0
#define MAIN_CH_IP_CUR_1P2A 0xB0
#define MAIN_CH_IP_CUR_1P3A 0xC0
#define MAIN_CH_IP_CUR_1P4A 0xD0
#define MAIN_CH_IP_CUR_1P5A 0xE0
/* ChVoltLevel */
#define CH_VOL_LVL_3P5 0x00
#define CH_VOL_LVL_4P0 0x14
#define CH_VOL_LVL_4P05 0x16
#define CH_VOL_LVL_4P1 0x1B
#define CH_VOL_LVL_4P15 0x20
#define CH_VOL_LVL_4P2 0x25
#define CH_VOL_LVL_4P6 0x4D
/* ChOutputCurrentLevel */
#define CH_OP_CUR_LVL_0P1 0x00
#define CH_OP_CUR_LVL_0P2 0x01
#define CH_OP_CUR_LVL_0P3 0x02
#define CH_OP_CUR_LVL_0P4 0x03
#define CH_OP_CUR_LVL_0P5 0x04
#define CH_OP_CUR_LVL_0P6 0x05
#define CH_OP_CUR_LVL_0P7 0x06
#define CH_OP_CUR_LVL_0P8 0x07
#define CH_OP_CUR_LVL_0P9 0x08
#define CH_OP_CUR_LVL_1P4 0x0D
#define CH_OP_CUR_LVL_1P5 0x0E
#define CH_OP_CUR_LVL_1P6 0x0F
/* BTEMP High thermal limits */
#define BTEMP_HIGH_TH_57_0 0x00
#define BTEMP_HIGH_TH_52 0x01
#define BTEMP_HIGH_TH_57_1 0x02
#define BTEMP_HIGH_TH_62 0x03
/* current is mA */
#define USB_0P1A 100
#define USB_0P2A 200
#define USB_0P3A 300
#define USB_0P4A 400
#define USB_0P5A 500
#define LOW_BAT_3P1V 0x20
#define LOW_BAT_2P3V 0x00
#define LOW_BAT_RESET 0x01
#define LOW_BAT_ENABLE 0x01
/* Backup battery constants */
#define BUP_ICH_SEL_50UA 0x00
#define BUP_ICH_SEL_150UA 0x04
#define BUP_ICH_SEL_300UA 0x08
#define BUP_ICH_SEL_700UA 0x0C
#define BUP_VCH_SEL_2P5V 0x00
#define BUP_VCH_SEL_2P6V 0x01
#define BUP_VCH_SEL_2P8V 0x02
#define BUP_VCH_SEL_3P1V 0x03
/* Battery OVV constants */
#define BATT_OVV_ENA 0x02
#define BATT_OVV_TH_3P7 0x00
#define BATT_OVV_TH_4P75 0x01
/* A value to indicate over voltage */
#define BATT_OVV_VALUE 4750
/* VBUS OVV constants */
#define VBUS_OVV_SELECT_MASK 0x78
#define VBUS_OVV_SELECT_5P6V 0x00
#define VBUS_OVV_SELECT_5P7V 0x08
#define VBUS_OVV_SELECT_5P8V 0x10
#define VBUS_OVV_SELECT_5P9V 0x18
#define VBUS_OVV_SELECT_6P0V 0x20
#define VBUS_OVV_SELECT_6P1V 0x28
#define VBUS_OVV_SELECT_6P2V 0x30
#define VBUS_OVV_SELECT_6P3V 0x38
#define VBUS_AUTO_IN_CURR_LIM_ENA 0x04
/* Fuel Gauge constants */
#define RESET_ACCU 0x02
#define READ_REQ 0x01
#define CC_DEEP_SLEEP_ENA 0x02
#define CC_PWR_UP_ENA 0x01
#define CC_SAMPLES_40 0x28
#define RD_NCONV_ACCU_REQ 0x01
#define CC_CALIB 0x08
#define CC_INTAVGOFFSET_ENA 0x10
#define CC_MUXOFFSET 0x80
#define CC_INT_CAL_N_AVG_MASK 0x60
#define CC_INT_CAL_SAMPLES_16 0x40
#define CC_INT_CAL_SAMPLES_8 0x20
#define CC_INT_CAL_SAMPLES_4 0x00
/* RTC constants */
#define RTC_BUP_CH_ENA 0x10
/* BatCtrl Current Source Constants */
#define BAT_CTRL_7U_ENA 0x01
#define BAT_CTRL_20U_ENA 0x02
#define BAT_CTRL_CMP_ENA 0x04
#define FORCE_BAT_CTRL_CMP_HIGH 0x08
#define BAT_CTRL_PULL_UP_ENA 0x10
/* Battery type */
#define BATTERY_UNKNOWN 00
/**
* struct res_to_temp - defines one point in a temp to res curve. To
* be used in battery packs that combines the identification resistor with a
* NTC resistor.
* @temp: battery pack temperature in Celcius
* @resist: NTC resistor net total resistance
*/
struct res_to_temp {
int temp;
int resist;
};
/**
* struct batres_vs_temp - defines one point in a temp vs battery internal
* resistance curve.
* @temp: battery pack temperature in Celcius
* @resist: battery internal reistance in mOhm
*/
struct batres_vs_temp {
int temp;
int resist;
};
/* Forward declaration */
struct ab8500_fg;
/**
* struct ab8500_fg_parameters - Fuel gauge algorithm parameters, in seconds
* if not specified
* @recovery_sleep_timer: Time between measurements while recovering
* @recovery_total_time: Total recovery time
* @init_timer: Measurement interval during startup
* @init_discard_time: Time we discard voltage measurement at startup
* @init_total_time: Total init time during startup
* @high_curr_time: Time current has to be high to go to recovery
* @accu_charging: FG accumulation time while charging
* @accu_high_curr: FG accumulation time in high current mode
* @high_curr_threshold: High current threshold, in mA
* @lowbat_threshold: Low battery threshold, in mV
* @battok_falling_th_sel0 Threshold in mV for battOk signal sel0
* Resolution in 50 mV step.
* @battok_raising_th_sel1 Threshold in mV for battOk signal sel1
* Resolution in 50 mV step.
* @user_cap_limit Capacity reported from user must be within this
* limit to be considered as sane, in percentage
* points.
* @maint_thres This is the threshold where we stop reporting
* battery full while in maintenance, in per cent
*/
struct ab8500_fg_parameters {
int recovery_sleep_timer;
int recovery_total_time;
int init_timer;
int init_discard_time;
int init_total_time;
int high_curr_time;
int accu_charging;
int accu_high_curr;
int high_curr_threshold;
int lowbat_threshold;
int battok_falling_th_sel0;
int battok_raising_th_sel1;
int user_cap_limit;
int maint_thres;
};
/**
* struct ab8500_charger_maximization - struct used by the board config.
* @use_maxi: Enable maximization for this battery type
* @maxi_chg_curr: Maximum charger current allowed
* @maxi_wait_cycles: cycles to wait before setting charger current
* @charger_curr_step delta between two charger current settings (mA)
*/
struct ab8500_maxim_parameters {
bool ena_maxi;
int chg_curr;
int wait_cycles;
int charger_curr_step;
};
/**
* struct ab8500_bm_capacity_levels - ab8500 capacity level data
* @critical: critical capacity level in percent
* @low: low capacity level in percent
* @normal: normal capacity level in percent
* @high: high capacity level in percent
* @full: full capacity level in percent
*/
struct ab8500_bm_capacity_levels {
int critical;
int low;
int normal;
int high;
int full;
};
/**
* struct ab8500_bm_charger_parameters - Charger specific parameters
* @usb_volt_max: maximum allowed USB charger voltage in mV
* @usb_curr_max: maximum allowed USB charger current in mA
* @ac_volt_max: maximum allowed AC charger voltage in mV
* @ac_curr_max: maximum allowed AC charger current in mA
*/
struct ab8500_bm_charger_parameters {
int usb_volt_max;
int usb_curr_max;
int ac_volt_max;
int ac_curr_max;
};
/**
* struct ab8500_bm_data - ab8500 battery management data
* @temp_under under this temp, charging is stopped
* @temp_low between this temp and temp_under charging is reduced
* @temp_high between this temp and temp_over charging is reduced
* @temp_over over this temp, charging is stopped
* @temp_interval_chg temperature measurement interval in s when charging
* @temp_interval_nochg temperature measurement interval in s when not charging
* @main_safety_tmr_h safety timer for main charger
* @usb_safety_tmr_h safety timer for usb charger
* @bkup_bat_v voltage which we charge the backup battery with
* @bkup_bat_i current which we charge the backup battery with
* @no_maintenance indicates that maintenance charging is disabled
* @adc_therm placement of thermistor, batctrl or battemp adc
* @chg_unknown_bat flag to enable charging of unknown batteries
* @enable_overshoot flag to enable VBAT overshoot control
* @fg_res resistance of FG resistor in 0.1mOhm
* @n_btypes number of elements in array bat_type
* @batt_id index of the identified battery in array bat_type
* @interval_charging charge alg cycle period time when charging (sec)
* @interval_not_charging charge alg cycle period time when not charging (sec)
* @temp_hysteresis temperature hysteresis
* @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
* @maxi: maximization parameters
* @cap_levels capacity in percent for the different capacity levels
* @bat_type table of supported battery types
* @chg_params charger parameters
* @fg_params fuel gauge parameters
*/
struct ab8500_bm_data {
int temp_under;
int temp_low;
int temp_high;
int temp_over;
int temp_interval_chg;
int temp_interval_nochg;
int main_safety_tmr_h;
int usb_safety_tmr_h;
int bkup_bat_v;
int bkup_bat_i;
bool no_maintenance;
bool chg_unknown_bat;
bool enable_overshoot;
enum abx500_adc_therm adc_therm;
int fg_res;
int n_btypes;
int batt_id;
int interval_charging;
int interval_not_charging;
int temp_hysteresis;
int gnd_lift_resistance;
const struct ab8500_maxim_parameters *maxi;
const struct ab8500_bm_capacity_levels *cap_levels;
const struct ab8500_bm_charger_parameters *chg_params;
const struct ab8500_fg_parameters *fg_params;
};
struct ab8500_charger_platform_data {
char **supplied_to;
size_t num_supplicants;
bool autopower_cfg;
};
struct ab8500_btemp_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct ab8500_fg_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct ab8500_chargalg_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct ab8500_btemp;
struct ab8500_gpadc;
struct ab8500_fg;
#ifdef CONFIG_AB8500_BM
void ab8500_fg_reinit(void);
void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA);
struct ab8500_btemp *ab8500_btemp_get(void);
int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp);
struct ab8500_fg *ab8500_fg_get(void);
int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev);
int ab8500_fg_inst_curr_start(struct ab8500_fg *di);
int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res);
int ab8500_fg_inst_curr_done(struct ab8500_fg *di);
#else
int ab8500_fg_inst_curr_done(struct ab8500_fg *di)
{
}
static void ab8500_fg_reinit(void)
{
}
static void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA)
{
}
static struct ab8500_btemp *ab8500_btemp_get(void)
{
return NULL;
}
static int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp)
{
return 0;
}
struct ab8500_fg *ab8500_fg_get(void)
{
return NULL;
}
static int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev)
{
return -ENODEV;
}
static inline int ab8500_fg_inst_curr_start(struct ab8500_fg *di)
{
return -ENODEV;
}
static inline int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res)
{
return -ENODEV;
}
#endif
#endif /* _AB8500_BM_H */

4
include/linux/mfd/abx500/ab8500-gpio.h
View file

@ -10,12 +10,14 @@
/*
* Platform data to register a block: only the initial gpio/irq number.
* Array sizes are large enough to contain all AB8500 and AB9540 GPIO
* registers.
*/
struct ab8500_gpio_platform_data {
int gpio_base;
u32 irq_base;
u8 config_reg[7];
u8 config_reg[8];
};
#endif /* _AB8500_GPIO_H */

43
include/linux/mfd/abx500/ab8500-sysctrl.h
View file

@ -71,6 +71,13 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
#define AB8500_SWATCTRL 0x230
#define AB8500_HIQCLKCTRL 0x232
#define AB8500_VSIMSYSCLKCTRL 0x233
#define AB9540_SYSCLK12BUFCTRL 0x234
#define AB9540_SYSCLK12CONFCTRL 0x235
#define AB9540_SYSCLK12BUFCTRL2 0x236
#define AB9540_SYSCLK12BUF1VALID 0x237
#define AB9540_SYSCLK12BUF2VALID 0x238
#define AB9540_SYSCLK12BUF3VALID 0x239
#define AB9540_SYSCLK12BUF4VALID 0x23A
/* Bits */
#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
@ -251,4 +258,40 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
#endif /* __AB8500_SYSCTRL_H */

212
include/linux/mfd/abx500/ab8500.h
View file

@ -7,7 +7,32 @@
#ifndef MFD_AB8500_H
#define MFD_AB8500_H
#include <linux/device.h>
#include <linux/mutex.h>
struct device;
/*
* AB IC versions
*
* AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
* non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
* print of version string.
*/
enum ab8500_version {
AB8500_VERSION_AB8500 = 0x0,
AB8500_VERSION_AB8505 = 0x1,
AB8500_VERSION_AB9540 = 0x2,
AB8500_VERSION_AB8540 = 0x3,
AB8500_VERSION_UNDEFINED,
};
/* AB8500 CIDs*/
#define AB8500_CUTEARLY 0x00
#define AB8500_CUT1P0 0x10
#define AB8500_CUT1P1 0x11
#define AB8500_CUT2P0 0x20
#define AB8500_CUT3P0 0x30
#define AB8500_CUT3P3 0x33
/*
* AB8500 bank addresses
@ -35,30 +60,34 @@
/*
* Interrupts
* Values used to index into array ab8500_irq_regoffset[] defined in
* drivers/mdf/ab8500-core.c
*/
#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0
#define AB8500_INT_UN_PLUG_TV_DET 1
#define AB8500_INT_PLUG_TV_DET 2
/* Definitions for AB8500 and AB9540 */
/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */
#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */
#define AB8500_INT_TEMP_WARM 3
#define AB8500_INT_PON_KEY2DB_F 4
#define AB8500_INT_PON_KEY2DB_R 5
#define AB8500_INT_PON_KEY1DB_F 6
#define AB8500_INT_PON_KEY1DB_R 7
/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
#define AB8500_INT_BATT_OVV 8
#define AB8500_INT_MAIN_CH_UNPLUG_DET 10
#define AB8500_INT_MAIN_CH_PLUG_DET 11
#define AB8500_INT_USB_ID_DET_F 12
#define AB8500_INT_USB_ID_DET_R 13
#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */
#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */
#define AB8500_INT_VBUS_DET_F 14
#define AB8500_INT_VBUS_DET_R 15
/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
#define AB8500_INT_VBUS_CH_DROP_END 16
#define AB8500_INT_RTC_60S 17
#define AB8500_INT_RTC_ALARM 18
#define AB8500_INT_BAT_CTRL_INDB 20
#define AB8500_INT_CH_WD_EXP 21
#define AB8500_INT_VBUS_OVV 22
#define AB8500_INT_MAIN_CH_DROP_END 23
#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */
/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
#define AB8500_INT_CCN_CONV_ACC 24
#define AB8500_INT_INT_AUD 25
#define AB8500_INT_CCEOC 26
@ -67,7 +96,8 @@
#define AB8500_INT_LOW_BAT_R 29
#define AB8500_INT_BUP_CHG_NOT_OK 30
#define AB8500_INT_BUP_CHG_OK 31
#define AB8500_INT_GP_HW_ADC_CONV_END 32
/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */
#define AB8500_INT_ACC_DETECT_1DB_F 33
#define AB8500_INT_ACC_DETECT_1DB_R 34
#define AB8500_INT_ACC_DETECT_22DB_F 35
@ -75,38 +105,43 @@
#define AB8500_INT_ACC_DETECT_21DB_F 37
#define AB8500_INT_ACC_DETECT_21DB_R 38
#define AB8500_INT_GP_SW_ADC_CONV_END 39
#define AB8500_INT_GPIO6R 40
#define AB8500_INT_GPIO7R 41
#define AB8500_INT_GPIO8R 42
#define AB8500_INT_GPIO9R 43
/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */
#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */
#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */
#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */
#define AB8500_INT_GPIO10R 44
#define AB8500_INT_GPIO11R 45
#define AB8500_INT_GPIO12R 46
#define AB8500_INT_GPIO12R 46 /* not 8505 */
#define AB8500_INT_GPIO13R 47
#define AB8500_INT_GPIO24R 48
#define AB8500_INT_GPIO25R 49
#define AB8500_INT_GPIO36R 50
#define AB8500_INT_GPIO37R 51
#define AB8500_INT_GPIO38R 52
#define AB8500_INT_GPIO39R 53
/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
#define AB8500_INT_GPIO24R 48 /* not 8505 */
#define AB8500_INT_GPIO25R 49 /* not 8505 */
#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */
#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */
#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */
#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */
#define AB8500_INT_GPIO40R 54
#define AB8500_INT_GPIO41R 55
#define AB8500_INT_GPIO6F 56
#define AB8500_INT_GPIO7F 57
#define AB8500_INT_GPIO8F 58
#define AB8500_INT_GPIO9F 59
/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
#define AB8500_INT_GPIO10F 60
#define AB8500_INT_GPIO11F 61
#define AB8500_INT_GPIO12F 62
#define AB8500_INT_GPIO12F 62 /* not 8505 */
#define AB8500_INT_GPIO13F 63
#define AB8500_INT_GPIO24F 64
#define AB8500_INT_GPIO25F 65
#define AB8500_INT_GPIO36F 66
#define AB8500_INT_GPIO37F 67
#define AB8500_INT_GPIO38F 68
#define AB8500_INT_GPIO39F 69
/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
#define AB8500_INT_GPIO24F 64 /* not 8505 */
#define AB8500_INT_GPIO25F 65 /* not 8505 */
#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */
#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */
#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */
#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */
#define AB8500_INT_GPIO40F 70
#define AB8500_INT_GPIO41F 71
/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
#define AB8500_INT_ADP_SOURCE_ERROR 72
#define AB8500_INT_ADP_SINK_ERROR 73
#define AB8500_INT_ADP_PROBE_PLUG 74
@ -114,30 +149,67 @@
#define AB8500_INT_ADP_SENSE_OFF 76
#define AB8500_INT_USB_PHY_POWER_ERR 78
#define AB8500_INT_USB_LINK_STATUS 79
/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
#define AB8500_INT_BTEMP_LOW 80
#define AB8500_INT_BTEMP_LOW_MEDIUM 81
#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
#define AB8500_INT_BTEMP_HIGH 83
#define AB8500_INT_USB_CHARGER_NOT_OK 89
/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
#define AB8500_INT_SRP_DETECT 88
#define AB8500_INT_USB_CHARGER_NOT_OKR 89
#define AB8500_INT_ID_WAKEUP_R 90
#define AB8500_INT_ID_DET_R1R 92
#define AB8500_INT_ID_DET_R2R 93
#define AB8500_INT_ID_DET_R3R 94
#define AB8500_INT_ID_DET_R4R 95
/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
#define AB8500_INT_ID_WAKEUP_F 96
#define AB8500_INT_ID_DET_R1F 98
#define AB8500_INT_ID_DET_R2F 99
#define AB8500_INT_ID_DET_R3F 100
#define AB8500_INT_ID_DET_R4F 101
#define AB8500_INT_USB_CHG_DET_DONE 102
#define AB8500_INT_CHAUTORESTARTAFTSEC 102
#define AB8500_INT_CHSTOPBYSEC 103
/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
#define AB8500_INT_USB_CH_TH_PROT_F 104
#define AB8500_INT_USB_CH_TH_PROT_R 105
#define AB8500_INT_MAIN_CH_TH_PROT_F 106
#define AB8500_INT_MAIN_CH_TH_PROT_R 107
#define AB8500_INT_USB_CHARGER_NOT_OKF 111
#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
#define AB8500_INT_CHCURLIMNOHSCHIRP 109
#define AB8500_INT_CHCURLIMHSCHIRP 110
#define AB8500_INT_XTAL32K_KO 111
/* Definitions for AB9540 */
/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
#define AB9540_INT_GPIO50R 113
#define AB9540_INT_GPIO51R 114 /* not 8505 */
#define AB9540_INT_GPIO52R 115
#define AB9540_INT_GPIO53R 116
#define AB9540_INT_GPIO54R 117 /* not 8505 */
#define AB9540_INT_IEXT_CH_RF_BFN_R 118
#define AB9540_INT_IEXT_CH_RF_BFN_F 119
/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
#define AB9540_INT_GPIO50F 121
#define AB9540_INT_GPIO51F 122 /* not 8505 */
#define AB9540_INT_GPIO52F 123
#define AB9540_INT_GPIO53F 124
#define AB9540_INT_GPIO54F 125 /* not 8505 */
/*
* AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
* entire platform. This is a "compile time" constant so this must be set to
* the largest possible value that may be encountered with different AB SOCs.
* Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
* which is larger.
*/
#define AB8500_NR_IRQS 112
#define AB8505_NR_IRQS 128
#define AB9540_NR_IRQS 128
/* This is set to the roof of any AB8500 chip variant IRQ counts */
#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
#define AB8500_NUM_IRQ_REGS 14
#define AB9540_NUM_IRQ_REGS 17
/**
* struct ab8500 - ab8500 internal structure
@ -145,13 +217,18 @@
* @lock: read/write operations lock
* @irq_lock: genirq bus lock
* @irq: irq line
* @version: chip version id (e.g. ab8500 or ab9540)
* @chip_id: chip revision id
* @write: register write
* @write_masked: masked register write
* @read: register read
* @rx_buf: rx buf for SPI
* @tx_buf: tx buf for SPI
* @mask: cache of IRQ regs for bus lock
* @oldmask: cache of previous IRQ regs for bus lock
* @mask_size: Actual number of valid entries in mask[], oldmask[] and
* irq_reg_offset
* @irq_reg_offset: Array of offsets into IRQ registers
*/
struct ab8500 {
struct device *dev;
@ -160,16 +237,20 @@ struct ab8500 {
int irq_base;
int irq;
enum ab8500_version version;
u8 chip_id;
int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
int (*read) (struct ab8500 *a8500, u16 addr);
int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
int (*read)(struct ab8500 *ab8500, u16 addr);
unsigned long tx_buf[4];
unsigned long rx_buf[4];
u8 mask[AB8500_NUM_IRQ_REGS];
u8 oldmask[AB8500_NUM_IRQ_REGS];
u8 *mask;
u8 *oldmask;
int mask_size;
const int *irq_reg_offset;
};
struct regulator_reg_init;
@ -195,7 +276,52 @@ struct ab8500_platform_data {
struct ab8500_gpio_platform_data *gpio;
};
extern int __devinit ab8500_init(struct ab8500 *ab8500);
extern int __devinit ab8500_init(struct ab8500 *ab8500,
enum ab8500_version version);
extern int __devexit ab8500_exit(struct ab8500 *ab8500);
static inline int is_ab8500(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8500;
}
static inline int is_ab8505(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8505;
}
static inline int is_ab9540(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB9540;
}
static inline int is_ab8540(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8540;
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
}
#endif /* MFD_AB8500_H */

38
include/linux/mfd/abx500/ux500_chargalg.h Normal file
View file

@ -0,0 +1,38 @@
/*
* Copyright (C) ST-Ericsson SA 2012
* Author: Johan Gardsmark <johan.gardsmark@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL), version 2
*/
#ifndef _UX500_CHARGALG_H
#define _UX500_CHARGALG_H
#include <linux/power_supply.h>
#define psy_to_ux500_charger(x) container_of((x), \
struct ux500_charger, psy)
/* Forward declaration */
struct ux500_charger;
struct ux500_charger_ops {
int (*enable) (struct ux500_charger *, int, int, int);
int (*kick_wd) (struct ux500_charger *);
int (*update_curr) (struct ux500_charger *, int);
};
/**
* struct ux500_charger - power supply ux500 charger sub class
* @psy power supply base class
* @ops ux500 charger operations
* @max_out_volt maximum output charger voltage in mV
* @max_out_curr maximum output charger current in mA
*/
struct ux500_charger {
struct power_supply psy;
struct ux500_charger_ops ops;
int max_out_volt;
int max_out_curr;
};
#endif

40
include/linux/mfd/anatop.h Normal file
View file

@ -0,0 +1,40 @@
/*
* anatop.h - Anatop MFD driver
*
* Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
* Copyright (C) 2012 Linaro
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_ANATOP_H
#define __LINUX_MFD_ANATOP_H
#include <linux/spinlock.h>
/**
* anatop - MFD data
* @ioreg: ioremap register
* @reglock: spinlock for register read/write
*/
struct anatop {
void *ioreg;
spinlock_t reglock;
};
extern u32 anatop_get_bits(struct anatop *, u32, int, int);
extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
#endif /* __LINUX_MFD_ANATOP_H */

2
include/linux/mfd/da9052/da9052.h
View file

@ -76,8 +76,6 @@ enum da9052_chip_id {
struct da9052_pdata;
struct da9052 {
struct mutex io_lock;
struct device *dev;
struct regmap *regmap;

185
include/linux/mfd/db8500-prcmu.h
View file

@ -11,6 +11,24 @@
#define __MFD_DB8500_PRCMU_H
#include <linux/interrupt.h>
#include <linux/bitops.h>
/*
* Registers
*/
#define DB8500_PRCM_GPIOCR 0x138
#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0)
#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9)
#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11)
#define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23)
#define DB8500_PRCM_LINE_VALUE 0x170
#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
#define DB8500_PRCM_DSI_SW_RESET 0x324
#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
@ -421,40 +439,22 @@ enum auto_enable {
/* End of file previously known as prcmu-fw-defs_v1.h */
/**
* enum hw_acc_dev - enum for hw accelerators
* @HW_ACC_SVAMMDSP: for SVAMMDSP
* @HW_ACC_SVAPIPE: for SVAPIPE
* @HW_ACC_SIAMMDSP: for SIAMMDSP
* @HW_ACC_SIAPIPE: for SIAPIPE
* @HW_ACC_SGA: for SGA
* @HW_ACC_B2R2: for B2R2
* @HW_ACC_MCDE: for MCDE
* @HW_ACC_ESRAM1: for ESRAM1
* @HW_ACC_ESRAM2: for ESRAM2
* @HW_ACC_ESRAM3: for ESRAM3
* @HW_ACC_ESRAM4: for ESRAM4
* @NUM_HW_ACC: number of hardware accelerators
* enum prcmu_power_status - results from set_power_state
* @PRCMU_SLEEP_OK: Sleep went ok
* @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
* @PRCMU_IDLE_OK: Idle went ok
* @PRCMU_DEEPIDLE_OK: DeepIdle went ok
* @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
* @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
*
* Different hw accelerators which can be turned ON/
* OFF or put into retention (MMDSPs and ESRAMs).
* Used with EPOD API.
*
* NOTE! Deprecated, to be removed when all users switched over to use the
* regulator API.
*/
enum hw_acc_dev {
HW_ACC_SVAMMDSP,
HW_ACC_SVAPIPE,
HW_ACC_SIAMMDSP,
HW_ACC_SIAPIPE,
HW_ACC_SGA,
HW_ACC_B2R2,
HW_ACC_MCDE,
HW_ACC_ESRAM1,
HW_ACC_ESRAM2,
HW_ACC_ESRAM3,
HW_ACC_ESRAM4,
NUM_HW_ACC
enum prcmu_power_status {
PRCMU_SLEEP_OK = 0xf3,
PRCMU_DEEP_SLEEP_OK = 0xf6,
PRCMU_IDLE_OK = 0xf0,
PRCMU_DEEPIDLE_OK = 0xe3,
PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
PRCMU_ARMPENDINGIT_ER = 0x93,
};
/*
@ -493,6 +493,20 @@ struct prcmu_auto_pm_config {
u8 sva_policy;
};
#define PRCMU_FW_PROJECT_U8500 2
#define PRCMU_FW_PROJECT_U9500 4
#define PRCMU_FW_PROJECT_U8500_C2 7
#define PRCMU_FW_PROJECT_U9500_C2 11
#define PRCMU_FW_PROJECT_U8520 13
#define PRCMU_FW_PROJECT_U8420 14
struct prcmu_fw_version {
u8 project;
u8 api_version;
u8 func_version;
u8 errata;
};
#ifdef CONFIG_MFD_DB8500_PRCMU
void db8500_prcmu_early_init(void);
@ -500,42 +514,41 @@ int prcmu_set_rc_a2p(enum romcode_write);
enum romcode_read prcmu_get_rc_p2a(void);
enum ap_pwrst prcmu_get_xp70_current_state(void);
bool prcmu_has_arm_maxopp(void);
bool prcmu_is_u8400(void);
int prcmu_set_ape_opp(u8 opp);
int prcmu_get_ape_opp(void);
struct prcmu_fw_version *prcmu_get_fw_version(void);
int prcmu_request_ape_opp_100_voltage(bool enable);
int prcmu_release_usb_wakeup_state(void);
int prcmu_set_ddr_opp(u8 opp);
int prcmu_get_ddr_opp(void);
/* NOTE! Use regulator framework instead */
int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle);
bool prcmu_is_auto_pm_enabled(void);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
int prcmu_set_clock_divider(u8 clock, u8 divider);
int prcmu_config_hotdog(u8 threshold);
int prcmu_config_hotmon(u8 low, u8 high);
int prcmu_start_temp_sense(u16 cycles32k);
int prcmu_stop_temp_sense(void);
int db8500_prcmu_config_hotdog(u8 threshold);
int db8500_prcmu_config_hotmon(u8 low, u8 high);
int db8500_prcmu_start_temp_sense(u16 cycles32k);
int db8500_prcmu_stop_temp_sense(void);
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
void prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
void prcmu_modem_reset(void);
void prcmu_enable_spi2(void);
void prcmu_disable_spi2(void);
void db8500_prcmu_modem_reset(void);
int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
int prcmu_enable_a9wdog(u8 id);
int prcmu_disable_a9wdog(u8 id);
int prcmu_kick_a9wdog(u8 id);
int prcmu_load_a9wdog(u8 id, u32 val);
int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
int db8500_prcmu_enable_a9wdog(u8 id);
int db8500_prcmu_disable_a9wdog(u8 id);
int db8500_prcmu_kick_a9wdog(u8 id);
int db8500_prcmu_load_a9wdog(u8 id, u32 val);
void db8500_prcmu_system_reset(u16 reset_code);
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
u8 db8500_prcmu_get_power_state_result(void);
int db8500_prcmu_gic_decouple(void);
int db8500_prcmu_gic_recouple(void);
int db8500_prcmu_copy_gic_settings(void);
bool db8500_prcmu_gic_pending_irq(void);
bool db8500_prcmu_pending_irq(void);
bool db8500_prcmu_is_cpu_in_wfi(int cpu);
void db8500_prcmu_enable_wakeups(u32 wakeups);
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
int db8500_prcmu_request_clock(u8 clock, bool enable);
@ -549,6 +562,14 @@ u16 db8500_prcmu_get_reset_code(void);
bool db8500_prcmu_is_ac_wake_requested(void);
int db8500_prcmu_set_arm_opp(u8 opp);
int db8500_prcmu_get_arm_opp(void);
int db8500_prcmu_set_ape_opp(u8 opp);
int db8500_prcmu_get_ape_opp(void);
int db8500_prcmu_set_ddr_opp(u8 opp);
int db8500_prcmu_get_ddr_opp(void);
u32 db8500_prcmu_read(unsigned int reg);
void db8500_prcmu_write(unsigned int reg, u32 value);
void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
#else /* !CONFIG_MFD_DB8500_PRCMU */
@ -574,17 +595,17 @@ static inline bool prcmu_has_arm_maxopp(void)
return false;
}
static inline bool prcmu_is_u8400(void)
static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
{
return false;
return NULL;
}
static inline int prcmu_set_ape_opp(u8 opp)
static inline int db8500_prcmu_set_ape_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_ape_opp(void)
static inline int db8500_prcmu_get_ape_opp(void)
{
return APE_100_OPP;
}
@ -599,21 +620,16 @@ static inline int prcmu_release_usb_wakeup_state(void)
return 0;
}
static inline int prcmu_set_ddr_opp(u8 opp)
static inline int db8500_prcmu_set_ddr_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_ddr_opp(void)
static inline int db8500_prcmu_get_ddr_opp(void)
{
return DDR_100_OPP;
}
static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
{
return 0;
}
static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle)
{
@ -634,22 +650,22 @@ static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
return 0;
}
static inline int prcmu_config_hotdog(u8 threshold)
static inline int db8500_prcmu_config_hotdog(u8 threshold)
{
return 0;
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
{
return 0;
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
{
return 0;
}
static inline int prcmu_stop_temp_sense(void)
static inline int db8500_prcmu_stop_temp_sense(void)
{
return 0;
}
@ -668,17 +684,7 @@ static inline void prcmu_ac_wake_req(void) {}
static inline void prcmu_ac_sleep_req(void) {}
static inline void prcmu_modem_reset(void) {}
static inline int prcmu_enable_spi2(void)
{
return 0;
}
static inline int prcmu_disable_spi2(void)
{
return 0;
}
static inline void db8500_prcmu_modem_reset(void) {}
static inline void db8500_prcmu_system_reset(u16 reset_code) {}
@ -688,6 +694,11 @@ static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
return 0;
}
static inline u8 db8500_prcmu_get_power_state_result(void)
{
return 0;
}
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
@ -729,27 +740,27 @@ static inline u16 db8500_prcmu_get_reset_code(void)
return 0;
}
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
return 0;
}
static inline int prcmu_enable_a9wdog(u8 id)
static inline int db8500_prcmu_enable_a9wdog(u8 id)
{
return 0;
}
static inline int prcmu_disable_a9wdog(u8 id)
static inline int db8500_prcmu_disable_a9wdog(u8 id)
{
return 0;
}
static inline int prcmu_kick_a9wdog(u8 id)
static inline int db8500_prcmu_kick_a9wdog(u8 id)
{
return 0;
}
static inline int prcmu_load_a9wdog(u8 id, u32 val)
static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
{
return 0;
}
@ -769,6 +780,16 @@ static inline int db8500_prcmu_get_arm_opp(void)
return 0;
}
static inline u32 db8500_prcmu_read(unsigned int reg)
{
return 0;
}
static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
u32 value) {}
#endif /* !CONFIG_MFD_DB8500_PRCMU */
#endif /* __MFD_DB8500_PRCMU_H */

414
include/linux/mfd/dbx500-prcmu.h
View file

@ -10,7 +10,7 @@
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <asm/mach-types.h>
#include <linux/err.h>
/* PRCMU Wakeup defines */
enum prcmu_wakeup_index {
@ -80,6 +80,29 @@ enum prcmu_wakeup_index {
#define EPOD_STATE_ON_CLK_OFF 0x03
#define EPOD_STATE_ON 0x04
/* DB5500 CLKOUT IDs */
enum {
DB5500_CLKOUT0 = 0,
DB5500_CLKOUT1,
};
/* DB5500 CLKOUTx sources */
enum {
DB5500_CLKOUT_REF_CLK_SEL0,
DB5500_CLKOUT_RTC_CLK0_SEL0,
DB5500_CLKOUT_ULP_CLK_SEL0,
DB5500_CLKOUT_STATIC0,
DB5500_CLKOUT_REFCLK,
DB5500_CLKOUT_ULPCLK,
DB5500_CLKOUT_ARMCLK,
DB5500_CLKOUT_SYSACC0CLK,
DB5500_CLKOUT_SOC0PLLCLK,
DB5500_CLKOUT_SOC1PLLCLK,
DB5500_CLKOUT_DDRPLLCLK,
DB5500_CLKOUT_TVCLK,
DB5500_CLKOUT_IRDACLK,
};
/*
* CLKOUT sources
*/
@ -111,6 +134,7 @@ enum prcmu_clock {
PRCMU_MSP1CLK,
PRCMU_I2CCLK,
PRCMU_SDMMCCLK,
PRCMU_SPARE1CLK,
PRCMU_SLIMCLK,
PRCMU_PER1CLK,
PRCMU_PER2CLK,
@ -139,12 +163,20 @@ enum prcmu_clock {
PRCMU_IRRCCLK,
PRCMU_SIACLK,
PRCMU_SVACLK,
PRCMU_ACLK,
PRCMU_NUM_REG_CLOCKS,
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
PRCMU_CDCLK,
PRCMU_TIMCLK,
PRCMU_PLLSOC0,
PRCMU_PLLSOC1,
PRCMU_PLLDDR,
PRCMU_PLLDSI,
PRCMU_DSI0CLK,
PRCMU_DSI1CLK,
PRCMU_DSI0ESCCLK,
PRCMU_DSI1ESCCLK,
PRCMU_DSI2ESCCLK,
};
/**
@ -153,12 +185,14 @@ enum prcmu_clock {
* @APE_NO_CHANGE: The APE operating point is unchanged
* @APE_100_OPP: The new APE operating point is ape100opp
* @APE_50_OPP: 50%
* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
*/
enum ape_opp {
APE_OPP_INIT = 0x00,
APE_NO_CHANGE = 0x01,
APE_100_OPP = 0x02,
APE_50_OPP = 0x03
APE_50_OPP = 0x03,
APE_50_PARTLY_25_OPP = 0xFF,
};
/**
@ -218,9 +252,11 @@ enum ddr_pwrst {
#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
#include <mach/id.h>
static inline void __init prcmu_early_init(void)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_early_init();
else
return db8500_prcmu_early_init();
@ -229,7 +265,7 @@ static inline void __init prcmu_early_init(void)
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_set_power_state(state, keep_ulp_clk,
keep_ap_pll);
else
@ -237,9 +273,65 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
keep_ap_pll);
}
static inline u8 prcmu_get_power_state_result(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_power_state_result();
}
static inline int prcmu_gic_decouple(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_gic_decouple();
}
static inline int prcmu_gic_recouple(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_gic_recouple();
}
static inline bool prcmu_gic_pending_irq(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_gic_pending_irq();
}
static inline bool prcmu_is_cpu_in_wfi(int cpu)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_is_cpu_in_wfi(cpu);
}
static inline int prcmu_copy_gic_settings(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_copy_gic_settings();
}
static inline bool prcmu_pending_irq(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_pending_irq();
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_set_epod(epod_id, epod_state);
@ -247,7 +339,7 @@ static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
static inline void prcmu_enable_wakeups(u32 wakeups)
{
if (machine_is_u5500())
if (cpu_is_u5500())
db5500_prcmu_enable_wakeups(wakeups);
else
db8500_prcmu_enable_wakeups(wakeups);
@ -260,7 +352,7 @@ static inline void prcmu_disable_wakeups(void)
static inline void prcmu_config_abb_event_readout(u32 abb_events)
{
if (machine_is_u5500())
if (cpu_is_u5500())
db5500_prcmu_config_abb_event_readout(abb_events);
else
db8500_prcmu_config_abb_event_readout(abb_events);
@ -268,7 +360,7 @@ static inline void prcmu_config_abb_event_readout(u32 abb_events)
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
if (machine_is_u5500())
if (cpu_is_u5500())
db5500_prcmu_get_abb_event_buffer(buf);
else
db8500_prcmu_get_abb_event_buffer(buf);
@ -276,25 +368,40 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
static inline int prcmu_request_clock(u8 clock, bool enable)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_request_clock(clock, enable);
else
return db8500_prcmu_request_clock(clock, enable);
}
int prcmu_set_ape_opp(u8 opp);
int prcmu_get_ape_opp(void);
int prcmu_set_ddr_opp(u8 opp);
int prcmu_get_ddr_opp(void);
unsigned long prcmu_clock_rate(u8 clock);
long prcmu_round_clock_rate(u8 clock, unsigned long rate);
int prcmu_set_clock_rate(u8 clock, unsigned long rate);
static inline int prcmu_set_ddr_opp(u8 opp)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_set_ddr_opp(opp);
}
static inline int prcmu_get_ddr_opp(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_ddr_opp();
}
static inline int prcmu_set_arm_opp(u8 opp)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_set_arm_opp(opp);
@ -302,15 +409,31 @@ static inline int prcmu_set_arm_opp(u8 opp)
static inline int prcmu_get_arm_opp(void)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_arm_opp();
}
static inline int prcmu_set_ape_opp(u8 opp)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_set_ape_opp(opp);
}
static inline int prcmu_get_ape_opp(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_ape_opp();
}
static inline void prcmu_system_reset(u16 reset_code)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_system_reset(reset_code);
else
return db8500_prcmu_system_reset(reset_code);
@ -318,7 +441,7 @@ static inline void prcmu_system_reset(u16 reset_code)
static inline u16 prcmu_get_reset_code(void)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_get_reset_code();
else
return db8500_prcmu_get_reset_code();
@ -326,10 +449,17 @@ static inline u16 prcmu_get_reset_code(void)
void prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
void prcmu_modem_reset(void);
static inline void prcmu_modem_reset(void)
{
if (cpu_is_u5500())
return;
else
return db8500_prcmu_modem_reset();
}
static inline bool prcmu_is_ac_wake_requested(void)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_is_ac_wake_requested();
else
return db8500_prcmu_is_ac_wake_requested();
@ -337,7 +467,7 @@ static inline bool prcmu_is_ac_wake_requested(void)
static inline int prcmu_set_display_clocks(void)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_set_display_clocks();
else
return db8500_prcmu_set_display_clocks();
@ -345,7 +475,7 @@ static inline int prcmu_set_display_clocks(void)
static inline int prcmu_disable_dsipll(void)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_disable_dsipll();
else
return db8500_prcmu_disable_dsipll();
@ -353,7 +483,7 @@ static inline int prcmu_disable_dsipll(void)
static inline int prcmu_enable_dsipll(void)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return db5500_prcmu_enable_dsipll();
else
return db8500_prcmu_enable_dsipll();
@ -361,11 +491,107 @@ static inline int prcmu_enable_dsipll(void)
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
if (machine_is_u5500())
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_config_esram0_deep_sleep(state);
}
static inline int prcmu_config_hotdog(u8 threshold)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_config_hotdog(threshold);
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_config_hotmon(low, high);
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_start_temp_sense(cycles32k);
}
static inline int prcmu_stop_temp_sense(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_stop_temp_sense();
}
static inline u32 prcmu_read(unsigned int reg)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_read(reg);
}
static inline void prcmu_write(unsigned int reg, u32 value)
{
if (cpu_is_u5500())
return;
else
db8500_prcmu_write(reg, value);
}
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
if (cpu_is_u5500())
return;
else
db8500_prcmu_write_masked(reg, mask, value);
}
static inline int prcmu_enable_a9wdog(u8 id)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_enable_a9wdog(id);
}
static inline int prcmu_disable_a9wdog(u8 id)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_disable_a9wdog(id);
}
static inline int prcmu_kick_a9wdog(u8 id)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_kick_a9wdog(id);
}
static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_load_a9wdog(id, timeout);
}
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
}
#else
static inline void __init prcmu_early_init(void) {}
@ -395,6 +621,12 @@ static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
return -ENOSYS;
}
static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
u8 size)
{
return -ENOSYS;
}
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
return 0;
@ -405,6 +637,21 @@ static inline int prcmu_request_clock(u8 clock, bool enable)
return 0;
}
static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
{
return 0;
}
static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
{
return 0;
}
static inline unsigned long prcmu_clock_rate(u8 clock)
{
return 0;
}
static inline int prcmu_set_ape_opp(u8 opp)
{
return 0;
@ -480,14 +727,133 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
*buf = NULL;
}
static inline int prcmu_config_hotdog(u8 threshold)
{
return 0;
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
{
return 0;
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
{
return 0;
}
static inline int prcmu_stop_temp_sense(void)
{
return 0;
}
static inline u32 prcmu_read(unsigned int reg)
{
return 0;
}
static inline void prcmu_write(unsigned int reg, u32 value) {}
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
#endif
static inline void prcmu_set(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, bits);
}
static inline void prcmu_clear(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, 0);
}
#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
/**
* prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
*/
static inline void prcmu_enable_spi2(void)
{
if (cpu_is_u8500())
prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
}
/**
* prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
*/
static inline void prcmu_disable_spi2(void)
{
if (cpu_is_u8500())
prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
}
/**
* prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
* and UARTMOD on OtherAlternateC3.
*/
static inline void prcmu_enable_stm_mod_uart(void)
{
if (cpu_is_u8500()) {
prcmu_set(DB8500_PRCM_GPIOCR,
(DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
}
}
/**
* prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
* and UARTMOD on OtherAlternateC3.
*/
static inline void prcmu_disable_stm_mod_uart(void)
{
if (cpu_is_u8500()) {
prcmu_clear(DB8500_PRCM_GPIOCR,
(DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
}
}
/**
* prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
*/
static inline void prcmu_enable_stm_ape(void)
{
if (cpu_is_u8500()) {
prcmu_set(DB8500_PRCM_GPIOCR,
DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
}
}
/**
* prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
*/
static inline void prcmu_disable_stm_ape(void)
{
if (cpu_is_u8500()) {
prcmu_clear(DB8500_PRCM_GPIOCR,
DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
}
}
#else
static inline void prcmu_enable_spi2(void) {}
static inline void prcmu_disable_spi2(void) {}
static inline void prcmu_enable_stm_mod_uart(void) {}
static inline void prcmu_disable_stm_mod_uart(void) {}
static inline void prcmu_enable_stm_ape(void) {}
static inline void prcmu_disable_stm_ape(void) {}
#endif
/* PRCMU QoS APE OPP class */
#define PRCMU_QOS_APE_OPP 1
#define PRCMU_QOS_DDR_OPP 2
#define PRCMU_QOS_ARM_OPP 3
#define PRCMU_QOS_DEFAULT_VALUE -1
#ifdef CONFIG_UX500_PRCMU_QOS_POWER
#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);

53
include/linux/mfd/max8997.h
View file

@ -131,6 +131,55 @@ struct max8997_muic_platform_data {
int num_init_data;
};
enum max8997_haptic_motor_type {
MAX8997_HAPTIC_ERM,
MAX8997_HAPTIC_LRA,
};
enum max8997_haptic_pulse_mode {
MAX8997_EXTERNAL_MODE,
MAX8997_INTERNAL_MODE,
};
enum max8997_haptic_pwm_divisor {
MAX8997_PWM_DIVISOR_32,
MAX8997_PWM_DIVISOR_64,
MAX8997_PWM_DIVISOR_128,
MAX8997_PWM_DIVISOR_256,
};
/**
* max8997_haptic_platform_data
* @pwm_channel_id: channel number of PWM device
* valid for MAX8997_EXTERNAL_MODE
* @pwm_period: period in nano second for PWM device
* valid for MAX8997_EXTERNAL_MODE
* @type: motor type
* @mode: pulse mode
* MAX8997_EXTERNAL_MODE: external PWM device is used to control motor
* MAX8997_INTERNAL_MODE: internal pulse generator is used to control motor
* @pwm_divisor: divisor for external PWM device
* @internal_mode_pattern: internal mode pattern for internal mode
* [0 - 3]: valid pattern number
* @pattern_cycle: the number of cycles of the waveform
* for the internal mode pattern
* [0 - 15]: available cycles
* @pattern_signal_period: period of the waveform for the internal mode pattern
* [0 - 255]: available period
*/
struct max8997_haptic_platform_data {
unsigned int pwm_channel_id;
unsigned int pwm_period;
enum max8997_haptic_motor_type type;
enum max8997_haptic_pulse_mode mode;
enum max8997_haptic_pwm_divisor pwm_divisor;
unsigned int internal_mode_pattern;
unsigned int pattern_cycle;
unsigned int pattern_signal_period;
};
enum max8997_led_mode {
MAX8997_NONE,
MAX8997_FLASH_MODE,
@ -192,7 +241,9 @@ struct max8997_platform_data {
/* ---- MUIC ---- */
struct max8997_muic_platform_data *muic_pdata;
/* HAPTIC: Not implemented */
/* ---- HAPTIC ---- */
struct max8997_haptic_platform_data *haptic_pdata;
/* RTC: Not implemented */
/* ---- LED ---- */
struct max8997_led_platform_data *led_pdata;

16
include/linux/mfd/mc13xxx.h
View file

@ -38,7 +38,8 @@ int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
unsigned int mode, unsigned int channel, unsigned int *sample);
unsigned int mode, unsigned int channel,
u8 ato, bool atox, unsigned int *sample);
#define MC13XXX_IRQ_ADCDONE 0
#define MC13XXX_IRQ_ADCBISDONE 1
@ -157,6 +158,18 @@ struct mc13xxx_buttons_platform_data {
unsigned short b3on_key;
};
struct mc13xxx_ts_platform_data {
/* Delay between Touchscreen polarization and ADC Conversion.
* Given in clock ticks of a 32 kHz clock which gives a granularity of
* about 30.5ms */
u8 ato;
#define MC13783_TS_ATO_FIRST false
#define MC13783_TS_ATO_EACH true
/* Use the ATO delay only for the first conversion or for each one */
bool atox;
};
struct mc13xxx_platform_data {
#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
#define MC13XXX_USE_CODEC (1 << 1)
@ -167,6 +180,7 @@ struct mc13xxx_platform_data {
struct mc13xxx_regulator_platform_data regulators;
struct mc13xxx_leds_platform_data *leds;
struct mc13xxx_buttons_platform_data *buttons;
struct mc13xxx_ts_platform_data touch;
};
#define MC13XXX_ADC_MODE_TS 1

14
include/linux/mfd/mcp.h
View file

@ -10,8 +10,6 @@
#ifndef MCP_H
#define MCP_H
#include <mach/dma.h>
struct mcp_ops;
struct mcp {
@ -21,12 +19,7 @@ struct mcp {
int use_count;
unsigned int sclk_rate;
unsigned int rw_timeout;
dma_device_t dma_audio_rd;
dma_device_t dma_audio_wr;
dma_device_t dma_telco_rd;
dma_device_t dma_telco_wr;
struct device attached_device;
int gpio_base;
};
struct mcp_ops {
@ -47,15 +40,14 @@ void mcp_disable(struct mcp *);
#define mcp_get_sclk_rate(mcp) ((mcp)->sclk_rate)
struct mcp *mcp_host_alloc(struct device *, size_t);
int mcp_host_register(struct mcp *);
void mcp_host_unregister(struct mcp *);
int mcp_host_add(struct mcp *, void *);
void mcp_host_del(struct mcp *);
void mcp_host_free(struct mcp *);
struct mcp_driver {
struct device_driver drv;
int (*probe)(struct mcp *);
void (*remove)(struct mcp *);
int (*suspend)(struct mcp *, pm_message_t);
int (*resume)(struct mcp *);
};
int mcp_driver_register(struct mcp_driver *);

1
include/linux/mfd/pm8xxx/pm8921.h
View file

@ -18,7 +18,6 @@
#ifndef __MFD_PM8921_H
#define __MFD_PM8921_H
#include <linux/device.h>
#include <linux/mfd/pm8xxx/irq.h>
#define PM8921_NR_IRQS 256

295
include/linux/mfd/rc5t583.h Normal file
View file

@ -0,0 +1,295 @@
/*
* Core driver interface to access RICOH_RC5T583 power management chip.
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
* Author: Laxman dewangan <ldewangan@nvidia.com>
*
* Based on code
* Copyright (C) 2011 RICOH COMPANY,LTD
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef __LINUX_MFD_RC5T583_H
#define __LINUX_MFD_RC5T583_H
#include <linux/mutex.h>
#include <linux/types.h>
#define RC5T583_MAX_REGS 0xF8
/* Maximum number of main interrupts */
#define MAX_MAIN_INTERRUPT 5
#define RC5T583_MAX_GPEDGE_REG 2
#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
/* Interrupt enable register */
#define RC5T583_INT_EN_SYS1 0x19
#define RC5T583_INT_EN_SYS2 0x1D
#define RC5T583_INT_EN_DCDC 0x41
#define RC5T583_INT_EN_RTC 0xED
#define RC5T583_INT_EN_ADC1 0x90
#define RC5T583_INT_EN_ADC2 0x91
#define RC5T583_INT_EN_ADC3 0x92
/* Interrupt status registers (monitor regs in Ricoh)*/
#define RC5T583_INTC_INTPOL 0xAD
#define RC5T583_INTC_INTEN 0xAE
#define RC5T583_INTC_INTMON 0xAF
#define RC5T583_INT_MON_GRP 0xAF
#define RC5T583_INT_MON_SYS1 0x1B
#define RC5T583_INT_MON_SYS2 0x1F
#define RC5T583_INT_MON_DCDC 0x43
#define RC5T583_INT_MON_RTC 0xEE
/* Interrupt clearing registers */
#define RC5T583_INT_IR_SYS1 0x1A
#define RC5T583_INT_IR_SYS2 0x1E
#define RC5T583_INT_IR_DCDC 0x42
#define RC5T583_INT_IR_RTC 0xEE
#define RC5T583_INT_IR_ADCL 0x94
#define RC5T583_INT_IR_ADCH 0x95
#define RC5T583_INT_IR_ADCEND 0x96
#define RC5T583_INT_IR_GPIOR 0xA9
#define RC5T583_INT_IR_GPIOF 0xAA
/* Sleep sequence registers */
#define RC5T583_SLPSEQ1 0x21
#define RC5T583_SLPSEQ2 0x22
#define RC5T583_SLPSEQ3 0x23
#define RC5T583_SLPSEQ4 0x24
#define RC5T583_SLPSEQ5 0x25
#define RC5T583_SLPSEQ6 0x26
#define RC5T583_SLPSEQ7 0x27
#define RC5T583_SLPSEQ8 0x28
#define RC5T583_SLPSEQ9 0x29
#define RC5T583_SLPSEQ10 0x2A
#define RC5T583_SLPSEQ11 0x2B
/* Regulator registers */
#define RC5T583_REG_DC0CTL 0x30
#define RC5T583_REG_DC0DAC 0x31
#define RC5T583_REG_DC0LATCTL 0x32
#define RC5T583_REG_SR0CTL 0x33
#define RC5T583_REG_DC1CTL 0x34
#define RC5T583_REG_DC1DAC 0x35
#define RC5T583_REG_DC1LATCTL 0x36
#define RC5T583_REG_SR1CTL 0x37
#define RC5T583_REG_DC2CTL 0x38
#define RC5T583_REG_DC2DAC 0x39
#define RC5T583_REG_DC2LATCTL 0x3A
#define RC5T583_REG_SR2CTL 0x3B
#define RC5T583_REG_DC3CTL 0x3C
#define RC5T583_REG_DC3DAC 0x3D
#define RC5T583_REG_DC3LATCTL 0x3E
#define RC5T583_REG_SR3CTL 0x3F
#define RC5T583_REG_LDOEN1 0x50
#define RC5T583_REG_LDOEN2 0x51
#define RC5T583_REG_LDODIS1 0x52
#define RC5T583_REG_LDODIS2 0x53
#define RC5T583_REG_LDO0DAC 0x54
#define RC5T583_REG_LDO1DAC 0x55
#define RC5T583_REG_LDO2DAC 0x56
#define RC5T583_REG_LDO3DAC 0x57
#define RC5T583_REG_LDO4DAC 0x58
#define RC5T583_REG_LDO5DAC 0x59
#define RC5T583_REG_LDO6DAC 0x5A
#define RC5T583_REG_LDO7DAC 0x5B
#define RC5T583_REG_LDO8DAC 0x5C
#define RC5T583_REG_LDO9DAC 0x5D
#define RC5T583_REG_DC0DAC_DS 0x60
#define RC5T583_REG_DC1DAC_DS 0x61
#define RC5T583_REG_DC2DAC_DS 0x62
#define RC5T583_REG_DC3DAC_DS 0x63
#define RC5T583_REG_LDO0DAC_DS 0x64
#define RC5T583_REG_LDO1DAC_DS 0x65
#define RC5T583_REG_LDO2DAC_DS 0x66
#define RC5T583_REG_LDO3DAC_DS 0x67
#define RC5T583_REG_LDO4DAC_DS 0x68
#define RC5T583_REG_LDO5DAC_DS 0x69
#define RC5T583_REG_LDO6DAC_DS 0x6A
#define RC5T583_REG_LDO7DAC_DS 0x6B
#define RC5T583_REG_LDO8DAC_DS 0x6C
#define RC5T583_REG_LDO9DAC_DS 0x6D
/* GPIO register base address */
#define RC5T583_GPIO_IOSEL 0xA0
#define RC5T583_GPIO_PDEN 0xA1
#define RC5T583_GPIO_IOOUT 0xA2
#define RC5T583_GPIO_PGSEL 0xA3
#define RC5T583_GPIO_GPINV 0xA4
#define RC5T583_GPIO_GPDEB 0xA5
#define RC5T583_GPIO_GPEDGE1 0xA6
#define RC5T583_GPIO_GPEDGE2 0xA7
#define RC5T583_GPIO_EN_INT 0xA8
#define RC5T583_GPIO_MON_IOIN 0xAB
#define RC5T583_GPIO_GPOFUNC 0xAC
/* RICOH_RC5T583 IRQ definitions */
enum {
RC5T583_IRQ_ONKEY,
RC5T583_IRQ_ACOK,
RC5T583_IRQ_LIDOPEN,
RC5T583_IRQ_PREOT,
RC5T583_IRQ_CLKSTP,
RC5T583_IRQ_ONKEY_OFF,
RC5T583_IRQ_WD,
RC5T583_IRQ_EN_PWRREQ1,
RC5T583_IRQ_EN_PWRREQ2,
RC5T583_IRQ_PRE_VINDET,
RC5T583_IRQ_DC0LIM,
RC5T583_IRQ_DC1LIM,
RC5T583_IRQ_DC2LIM,
RC5T583_IRQ_DC3LIM,
RC5T583_IRQ_CTC,
RC5T583_IRQ_YALE,
RC5T583_IRQ_DALE,
RC5T583_IRQ_WALE,
RC5T583_IRQ_AIN1L,
RC5T583_IRQ_AIN2L,
RC5T583_IRQ_AIN3L,
RC5T583_IRQ_VBATL,
RC5T583_IRQ_VIN3L,
RC5T583_IRQ_VIN8L,
RC5T583_IRQ_AIN1H,
RC5T583_IRQ_AIN2H,
RC5T583_IRQ_AIN3H,
RC5T583_IRQ_VBATH,
RC5T583_IRQ_VIN3H,
RC5T583_IRQ_VIN8H,
RC5T583_IRQ_ADCEND,
RC5T583_IRQ_GPIO0,
RC5T583_IRQ_GPIO1,
RC5T583_IRQ_GPIO2,
RC5T583_IRQ_GPIO3,
RC5T583_IRQ_GPIO4,
RC5T583_IRQ_GPIO5,
RC5T583_IRQ_GPIO6,
RC5T583_IRQ_GPIO7,
/* Should be last entry */
RC5T583_MAX_IRQS,
};
/* Ricoh583 gpio definitions */
enum {
RC5T583_GPIO0,
RC5T583_GPIO1,
RC5T583_GPIO2,
RC5T583_GPIO3,
RC5T583_GPIO4,
RC5T583_GPIO5,
RC5T583_GPIO6,
RC5T583_GPIO7,
/* Should be last entry */
RC5T583_MAX_GPIO,
};
enum {
RC5T583_DS_NONE,
RC5T583_DS_DC0,
RC5T583_DS_DC1,
RC5T583_DS_DC2,
RC5T583_DS_DC3,
RC5T583_DS_LDO0,
RC5T583_DS_LDO1,
RC5T583_DS_LDO2,
RC5T583_DS_LDO3,
RC5T583_DS_LDO4,
RC5T583_DS_LDO5,
RC5T583_DS_LDO6,
RC5T583_DS_LDO7,
RC5T583_DS_LDO8,
RC5T583_DS_LDO9,
RC5T583_DS_PSO0,
RC5T583_DS_PSO1,
RC5T583_DS_PSO2,
RC5T583_DS_PSO3,
RC5T583_DS_PSO4,
RC5T583_DS_PSO5,
RC5T583_DS_PSO6,
RC5T583_DS_PSO7,
/* Should be last entry */
RC5T583_DS_MAX,
};
/*
* Ricoh pmic RC5T583 supports sleep through two external controls.
* The output of gpios and regulator can be enable/disable through
* this external signals.
*/
enum {
RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
};
struct rc5t583 {
struct device *dev;
struct regmap *regmap;
int chip_irq;
int irq_base;
struct mutex irq_lock;
unsigned long group_irq_en[MAX_MAIN_INTERRUPT];
/* For main interrupt bits in INTC */
uint8_t intc_inten_reg;
/* For group interrupt bits and address */
uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
/* For gpio edge */
uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
};
/*
* rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
* The board specific data is provided through this structure.
* @irq_base: Irq base number on which this device registers their interrupts.
* @enable_shutdown: Enable shutdown through the input pin "shutdown".
*/
struct rc5t583_platform_data {
int irq_base;
bool enable_shutdown;
};
int rc5t583_write(struct device *dev, u8 reg, uint8_t val);
int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val);
int rc5t583_set_bits(struct device *dev, unsigned int reg,
unsigned int bit_mask);
int rc5t583_clear_bits(struct device *dev, unsigned int reg,
unsigned int bit_mask);
int rc5t583_update(struct device *dev, unsigned int reg,
unsigned int val, unsigned int mask);
int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
int ext_pwr_req, int deepsleep_slot_nr);
int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
int rc5t583_irq_exit(struct rc5t583 *rc5t583);
#endif

5
include/linux/mfd/stmpe.h
View file

@ -8,7 +8,9 @@
#ifndef __LINUX_MFD_STMPE_H
#define __LINUX_MFD_STMPE_H
#include <linux/device.h>
#include <linux/mutex.h>
struct device;
enum stmpe_block {
STMPE_BLOCK_GPIO = 1 << 0,
@ -26,6 +28,7 @@ enum stmpe_partnum {
STMPE1601,
STMPE2401,
STMPE2403,
STMPE_NBR_PARTS
};
/*

2
include/linux/mfd/tc3589x.h
View file

@ -7,7 +7,7 @@
#ifndef __LINUX_MFD_TC3589x_H
#define __LINUX_MFD_TC3589x_H
#include <linux/device.h>
struct device;
enum tx3589x_block {
TC3589x_BLOCK_GPIO = 1 << 0,

26
include/linux/mfd/tmio.h
View file

@ -1,8 +1,10 @@
#ifndef MFD_TMIO_H
#define MFD_TMIO_H
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
@ -64,8 +66,8 @@
#define TMIO_MMC_SDIO_IRQ (1 << 2)
/*
* Some platforms can detect card insertion events with controller powered
* down, in which case they have to call tmio_mmc_cd_wakeup() to power up the
* controller and report the event to the driver.
* down, using a GPIO IRQ, in which case they have to fill in cd_irq, cd_gpio,
* and cd_flags fields of struct tmio_mmc_data.
*/
#define TMIO_MMC_HAS_COLD_CD (1 << 3)
/*
@ -73,6 +75,12 @@
* idle before writing to some registers.
*/
#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
/*
* A GPIO is used for card hotplug detection. We need an extra flag for this,
* because 0 is a valid GPIO number too, and requiring users to specify
* cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
*/
#define TMIO_MMC_USE_GPIO_CD (1 << 5)
int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@ -97,19 +105,23 @@ struct tmio_mmc_data {
u32 ocr_mask; /* available voltages */
struct tmio_mmc_dma *dma;
struct device *dev;
bool power;
unsigned int cd_gpio;
void (*set_pwr)(struct platform_device *host, int state);
void (*set_clk_div)(struct platform_device *host, int state);
int (*get_cd)(struct platform_device *host);
int (*write16_hook)(struct tmio_mmc_host *host, int addr);
};
/*
* This function is deprecated and will be removed soon. Please, convert your
* platform to use drivers/mmc/core/cd-gpio.c
*/
#include <linux/mmc/host.h>
static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
{
if (pdata && !pdata->power) {
pdata->power = true;
pm_runtime_get(pdata->dev);
}
if (pdata)
mmc_detect_change(dev_get_drvdata(pdata->dev),
msecs_to_jiffies(100));
}
/*

46
include/linux/mfd/tps65090.h Normal file
View file

@ -0,0 +1,46 @@
/*
* Core driver interface for TI TPS65090 PMIC family
*
* Copyright (C) 2012 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
*/
#ifndef __LINUX_MFD_TPS65090_H
#define __LINUX_MFD_TPS65090_H
struct tps65090_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct tps65090_platform_data {
int irq_base;
int num_subdevs;
struct tps65090_subdev_info *subdevs;
};
/*
* NOTE: the functions below are not intended for use outside
* of the TPS65090 sub-device drivers
*/
extern int tps65090_write(struct device *dev, int reg, uint8_t val);
extern int tps65090_read(struct device *dev, int reg, uint8_t *val);
extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num);
extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num);
#endif /*__LINUX_MFD_TPS65090_H */

283
include/linux/mfd/tps65217.h Normal file
View file

@ -0,0 +1,283 @@
/*
* linux/mfd/tps65217.h
*
* Functions to access TPS65217 power management chip.
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_MFD_TPS65217_H
#define __LINUX_MFD_TPS65217_H
#include <linux/i2c.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
/* I2C ID for TPS65217 part */
#define TPS65217_I2C_ID 0x24
/* All register addresses */
#define TPS65217_REG_CHIPID 0X00
#define TPS65217_REG_PPATH 0X01
#define TPS65217_REG_INT 0X02
#define TPS65217_REG_CHGCONFIG0 0X03
#define TPS65217_REG_CHGCONFIG1 0X04
#define TPS65217_REG_CHGCONFIG2 0X05
#define TPS65217_REG_CHGCONFIG3 0X06
#define TPS65217_REG_WLEDCTRL1 0X07
#define TPS65217_REG_WLEDCTRL2 0X08
#define TPS65217_REG_MUXCTRL 0X09
#define TPS65217_REG_STATUS 0X0A
#define TPS65217_REG_PASSWORD 0X0B
#define TPS65217_REG_PGOOD 0X0C
#define TPS65217_REG_DEFPG 0X0D
#define TPS65217_REG_DEFDCDC1 0X0E
#define TPS65217_REG_DEFDCDC2 0X0F
#define TPS65217_REG_DEFDCDC3 0X10
#define TPS65217_REG_DEFSLEW 0X11
#define TPS65217_REG_DEFLDO1 0X12
#define TPS65217_REG_DEFLDO2 0X13
#define TPS65217_REG_DEFLS1 0X14
#define TPS65217_REG_DEFLS2 0X15
#define TPS65217_REG_ENABLE 0X16
#define TPS65217_REG_DEFUVLO 0X18
#define TPS65217_REG_SEQ1 0X19
#define TPS65217_REG_SEQ2 0X1A
#define TPS65217_REG_SEQ3 0X1B
#define TPS65217_REG_SEQ4 0X1C
#define TPS65217_REG_SEQ5 0X1D
#define TPS65217_REG_SEQ6 0X1E
/* Register field definitions */
#define TPS65217_CHIPID_CHIP_MASK 0xF0
#define TPS65217_CHIPID_REV_MASK 0x0F
#define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
#define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
#define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
#define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
#define TPS65217_PPATH_USB_CURRENT_MASK 0x03
#define TPS65217_INT_PBM BIT(6)
#define TPS65217_INT_ACM BIT(5)
#define TPS65217_INT_USBM BIT(4)
#define TPS65217_INT_PBI BIT(2)
#define TPS65217_INT_ACI BIT(1)
#define TPS65217_INT_USBI BIT(0)
#define TPS65217_CHGCONFIG0_TREG BIT(7)
#define TPS65217_CHGCONFIG0_DPPM BIT(6)
#define TPS65217_CHGCONFIG0_TSUSP BIT(5)
#define TPS65217_CHGCONFIG0_TERMI BIT(4)
#define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
#define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
#define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
#define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
#define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
#define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
#define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
#define TPS65217_CHGCONFIG1_RESET BIT(3)
#define TPS65217_CHGCONFIG1_TERM BIT(2)
#define TPS65217_CHGCONFIG1_SUSP BIT(1)
#define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
#define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
#define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
#define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
#define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
#define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
#define TPS65217_CHGCONFIG2_TERMIF 0x06
#define TPS65217_CHGCONFIG2_TRANGE BIT(0)
#define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
#define TPS65217_WLEDCTRL1_ISEL BIT(2)
#define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
#define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
#define TPS65217_MUXCTRL_MUX_MASK 0x07
#define TPS65217_STATUS_OFF BIT(7)
#define TPS65217_STATUS_ACPWR BIT(3)
#define TPS65217_STATUS_USBPWR BIT(2)
#define TPS65217_STATUS_PB BIT(0)
#define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
#define TPS65217_PGOOD_LDO3_PG BIT(6)
#define TPS65217_PGOOD_LDO4_PG BIT(5)
#define TPS65217_PGOOD_DC1_PG BIT(4)
#define TPS65217_PGOOD_DC2_PG BIT(3)
#define TPS65217_PGOOD_DC3_PG BIT(2)
#define TPS65217_PGOOD_LDO1_PG BIT(1)
#define TPS65217_PGOOD_LDO2_PG BIT(0)
#define TPS65217_DEFPG_LDO1PGM BIT(3)
#define TPS65217_DEFPG_LDO2PGM BIT(2)
#define TPS65217_DEFPG_PGDLY_MASK 0x03
#define TPS65217_DEFDCDCX_XADJX BIT(7)
#define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
#define TPS65217_DEFSLEW_GO BIT(7)
#define TPS65217_DEFSLEW_GODSBL BIT(6)
#define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
#define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
#define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
#define TPS65217_DEFSLEW_SLEW_MASK 0x07
#define TPS65217_DEFLDO1_LDO1_MASK 0x0F
#define TPS65217_DEFLDO2_TRACK BIT(6)
#define TPS65217_DEFLDO2_LDO2_MASK 0x3F
#define TPS65217_DEFLDO3_LDO3_EN BIT(5)
#define TPS65217_DEFLDO3_LDO3_MASK 0x1F
#define TPS65217_DEFLDO4_LDO4_EN BIT(5)
#define TPS65217_DEFLDO4_LDO4_MASK 0x1F
#define TPS65217_ENABLE_LS1_EN BIT(6)
#define TPS65217_ENABLE_LS2_EN BIT(5)
#define TPS65217_ENABLE_DC1_EN BIT(4)
#define TPS65217_ENABLE_DC2_EN BIT(3)
#define TPS65217_ENABLE_DC3_EN BIT(2)
#define TPS65217_ENABLE_LDO1_EN BIT(1)
#define TPS65217_ENABLE_LDO2_EN BIT(0)
#define TPS65217_DEFUVLO_UVLOHYS BIT(2)
#define TPS65217_DEFUVLO_UVLO_MASK 0x03
#define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
#define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
#define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
#define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
#define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
#define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
#define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
#define TPS65217_SEQ5_DLY1_MASK 0xC0
#define TPS65217_SEQ5_DLY2_MASK 0x30
#define TPS65217_SEQ5_DLY3_MASK 0x0C
#define TPS65217_SEQ5_DLY4_MASK 0x03
#define TPS65217_SEQ6_DLY5_MASK 0xC0
#define TPS65217_SEQ6_DLY6_MASK 0x30
#define TPS65217_SEQ6_SEQUP BIT(2)
#define TPS65217_SEQ6_SEQDWN BIT(1)
#define TPS65217_SEQ6_INSTDWN BIT(0)
#define TPS65217_MAX_REGISTER 0x1E
#define TPS65217_PROTECT_NONE 0
#define TPS65217_PROTECT_L1 1
#define TPS65217_PROTECT_L2 2
enum tps65217_regulator_id {
/* DCDC's */
TPS65217_DCDC_1,
TPS65217_DCDC_2,
TPS65217_DCDC_3,
/* LDOs */
TPS65217_LDO_1,
TPS65217_LDO_2,
TPS65217_LDO_3,
TPS65217_LDO_4,
};
#define TPS65217_MAX_REG_ID TPS65217_LDO_4
/* Number of step-down converters available */
#define TPS65217_NUM_DCDC 3
/* Number of LDO voltage regulators available */
#define TPS65217_NUM_LDO 4
/* Number of total regulators available */
#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
/**
* struct tps65217_board - packages regulator init data
* @tps65217_regulator_data: regulator initialization values
*
* Board data may be used to initialize regulator.
*/
struct tps65217_board {
struct regulator_init_data *tps65217_init_data;
};
/**
* struct tps_info - packages regulator constraints
* @name: Voltage regulator name
* @min_uV: minimum micro volts
* @max_uV: minimum micro volts
* @vsel_to_uv: Function pointer to get voltage from selector
* @uv_to_vsel: Function pointer to get selector from voltage
* @table: Table for non-uniform voltage step-size
* @table_len: Length of the voltage table
* @enable_mask: Regulator enable mask bits
* @set_vout_reg: Regulator output voltage set register
* @set_vout_mask: Regulator output voltage set mask
*
* This data is used to check the regualtor voltage limits while setting.
*/
struct tps_info {
const char *name;
int min_uV;
int max_uV;
int (*vsel_to_uv)(unsigned int vsel);
int (*uv_to_vsel)(int uV, unsigned int *vsel);
const int *table;
unsigned int table_len;
unsigned int enable_mask;
unsigned int set_vout_reg;
unsigned int set_vout_mask;
};
/**
* struct tps65217 - tps65217 sub-driver chip access routines
*
* Device data may be used to access the TPS65217 chip
*/
struct tps65217 {
struct device *dev;
struct tps65217_board *pdata;
struct regulator_desc desc[TPS65217_NUM_REGULATOR];
struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
struct tps_info *info[TPS65217_NUM_REGULATOR];
struct regmap *regmap;
/* Client devices */
struct platform_device *regulator_pdev[TPS65217_NUM_REGULATOR];
};
static inline struct tps65217 *dev_to_tps65217(struct device *dev)
{
return dev_get_drvdata(dev);
}
int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
unsigned int *val);
int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
unsigned int val, unsigned int level);
int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int val, unsigned int level);
int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int level);
#endif /* __LINUX_MFD_TPS65217_H */

18
include/linux/mfd/tps65910.h
View file

@ -17,6 +17,8 @@
#ifndef __LINUX_MFD_TPS65910_H
#define __LINUX_MFD_TPS65910_H
#include <linux/gpio.h>
/* TPS chip id list */
#define TPS65910 0
#define TPS65911 1
@ -657,6 +659,8 @@
/*Register GPIO (0x80) register.RegisterDescription */
#define GPIO_SLEEP_MASK 0x80
#define GPIO_SLEEP_SHIFT 7
#define GPIO_DEB_MASK 0x10
#define GPIO_DEB_SHIFT 4
#define GPIO_PUEN_MASK 0x08
@ -740,6 +744,11 @@
#define TPS65910_GPIO_STS BIT(1)
#define TPS65910_GPIO_SET BIT(0)
/* Max number of TPS65910/11 GPIOs */
#define TPS65910_NUM_GPIO 6
#define TPS65911_NUM_GPIO 9
#define TPS6591X_MAX_NUM_GPIO 9
/* Regulator Index Definitions */
#define TPS65910_REG_VRTC 0
#define TPS65910_REG_VIO 1
@ -768,6 +777,12 @@
/* Max number of TPS65910/11 regulators */
#define TPS65910_NUM_REGS 13
/* External sleep controls through EN1/EN2/EN3/SLEEP inputs */
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4
#define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8
/**
* struct tps65910_board
* Board platform data may be used to initialize regulators.
@ -779,6 +794,8 @@ struct tps65910_board {
int irq_base;
int vmbch_threshold;
int vmbch2_threshold;
bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
};
@ -789,6 +806,7 @@ struct tps65910_board {
struct tps65910 {
struct device *dev;
struct i2c_client *i2c_client;
struct regmap *regmap;
struct mutex io_mutex;
unsigned int id;
int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);

2
include/linux/mfd/twl6040.h
View file

@ -187,8 +187,10 @@ struct twl6040 {
int rev;
u8 vibra_ctrl_cache[2];
/* PLL configuration */
int pll;
unsigned int sysclk;
unsigned int mclk;
unsigned int irq;
unsigned int irq_base;

38
include/linux/mfd/ucb1x00.h
View file

@ -12,7 +12,7 @@
#include <linux/mfd/mcp.h>
#include <linux/gpio.h>
#include <linux/semaphore.h>
#include <linux/mutex.h>
#define UCB_IO_DATA 0x00
#define UCB_IO_DIR 0x01
@ -104,17 +104,27 @@
#define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
#define UCB_MODE_AUD_OFF_CAN (1 << 13)
enum ucb1x00_reset {
UCB_RST_PROBE,
UCB_RST_RESUME,
UCB_RST_SUSPEND,
UCB_RST_REMOVE,
UCB_RST_PROBE_FAIL,
};
struct ucb1x00_irq {
void *devid;
void (*fn)(int, void *);
struct ucb1x00_plat_data {
void (*reset)(enum ucb1x00_reset);
unsigned irq_base;
int gpio_base;
unsigned can_wakeup;
};
struct ucb1x00 {
spinlock_t lock;
raw_spinlock_t irq_lock;
struct mcp *mcp;
unsigned int irq;
struct semaphore adc_sem;
int irq_base;
struct mutex adc_mutex;
spinlock_t io_lock;
u16 id;
u16 io_dir;
@ -122,7 +132,8 @@ struct ucb1x00 {
u16 adc_cr;
u16 irq_fal_enbl;
u16 irq_ris_enbl;
struct ucb1x00_irq irq_handler[16];
u16 irq_mask;
u16 irq_wake;
struct device dev;
struct list_head node;
struct list_head devs;
@ -144,7 +155,7 @@ struct ucb1x00_driver {
struct list_head devs;
int (*add)(struct ucb1x00_dev *dev);
void (*remove)(struct ucb1x00_dev *dev);
int (*suspend)(struct ucb1x00_dev *dev, pm_message_t state);
int (*suspend)(struct ucb1x00_dev *dev);
int (*resume)(struct ucb1x00_dev *dev);
};
@ -245,15 +256,4 @@ unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
void ucb1x00_adc_enable(struct ucb1x00 *ucb);
void ucb1x00_adc_disable(struct ucb1x00 *ucb);
/*
* Which edges of the IRQ do you want to control today?
*/
#define UCB_RISING (1 << 0)
#define UCB_FALLING (1 << 1)
int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid);
void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid);
#endif

4
include/linux/mfd/wm8994/pdata.h
View file

@ -22,7 +22,6 @@ struct wm8994_ldo_pdata {
/** GPIOs to enable regulator, 0 or less if not available */
int enable;
const char *supply;
const struct regulator_init_data *init_data;
};
@ -185,6 +184,9 @@ struct wm8994_pdata {
unsigned int jd_scthr:2;
unsigned int jd_thr:2;
/* Configure WM1811 jack detection for use with external capacitor */
unsigned int jd_ext_cap:1;
/* WM8958 microphone bias configuration */
int micbias[2];