MIPS: BMIPS: Delete the irqchip driver from irq.c
BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c. We no longer need this code under arch/mips. [ralf@linux-mips.org: Fix conflicts.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8853/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Kevin Cernekee
Ralf Baechle
parent
4b049a6b27
commit
e5a6fcc058
2 changed files with 19 additions and 211 deletions
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@ -1,37 +0,0 @@
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* Interrupt Controller
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Properties:
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- compatible: "brcm,bcm3384-intc"
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Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs.
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- reg: Address/length pairs for each mask/status register set. Length must
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be 8. If multiple register sets are specified, the first set will
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handle IRQ offsets 0..31, the second set 32..63, and so on.
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- interrupt-controller: This is an interrupt controller.
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- #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge
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or polarity configuration is possible with this controller.
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- interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or
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from another INTC.
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- interrupts: The IRQ on the parent controller.
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Example:
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periph_intc: periph_intc@14e00038 {
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compatible = "brcm,bcm3384-intc";
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/*
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* IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c
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* IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344
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*/
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reg = <0x14e00038 0x8 0x14e00340 0x8>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <4>;
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};
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@ -3,191 +3,36 @@
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Partially based on arch/mips/ralink/irq.c
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
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* Copyright (C) 2014 Broadcom Corporation
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* Author: Kevin Cernekee <cernekee@gmail.com>
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*/
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/irqchip.h>
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#include <asm/bmips.h>
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#include <asm/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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/* INTC register offsets */
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#define INTC_REG_ENABLE 0x00
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#define INTC_REG_STATUS 0x04
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#define MAX_WORDS 2
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#define IRQS_PER_WORD 32
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struct bcm3384_intc {
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int n_words;
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void __iomem *reg[MAX_WORDS];
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u32 enable[MAX_WORDS];
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spinlock_t lock;
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};
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static void bcm3384_intc_irq_unmask(struct irq_data *d)
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{
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struct bcm3384_intc *priv = d->domain->host_data;
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unsigned long flags;
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int idx = d->hwirq / IRQS_PER_WORD;
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int bit = d->hwirq % IRQS_PER_WORD;
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spin_lock_irqsave(&priv->lock, flags);
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priv->enable[idx] |= BIT(bit);
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__raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void bcm3384_intc_irq_mask(struct irq_data *d)
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{
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struct bcm3384_intc *priv = d->domain->host_data;
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unsigned long flags;
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int idx = d->hwirq / IRQS_PER_WORD;
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int bit = d->hwirq % IRQS_PER_WORD;
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spin_lock_irqsave(&priv->lock, flags);
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priv->enable[idx] &= ~BIT(bit);
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__raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static struct irq_chip bcm3384_intc_irq_chip = {
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.name = "INTC",
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.irq_unmask = bcm3384_intc_irq_unmask,
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.irq_mask = bcm3384_intc_irq_mask,
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.irq_mask_ack = bcm3384_intc_irq_mask,
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};
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#include <asm/time.h>
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unsigned int get_c0_compare_int(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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static void bcm3384_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_get_handler_data(irq);
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struct bcm3384_intc *priv = domain->host_data;
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unsigned long flags;
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unsigned int idx;
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for (idx = 0; idx < priv->n_words; idx++) {
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unsigned long pending;
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int hwirq;
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spin_lock_irqsave(&priv->lock, flags);
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pending = __raw_readl(priv->reg[idx] + INTC_REG_STATUS) &
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priv->enable[idx];
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spin_unlock_irqrestore(&priv->lock, flags);
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for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
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generic_handle_irq(irq_find_mapping(domain,
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hwirq + idx * IRQS_PER_WORD));
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}
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending =
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(read_c0_status() & read_c0_cause() & ST0_IM) >> STATUSB_IP0;
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int bit;
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for_each_set_bit(bit, &pending, 8)
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do_IRQ(MIPS_CPU_IRQ_BASE + bit);
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}
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static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &bcm3384_intc_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = intc_map,
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};
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static int __init ioremap_one_pair(struct bcm3384_intc *priv,
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struct device_node *node,
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int idx)
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{
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struct resource res;
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if (of_address_to_resource(node, idx, &res))
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return 0;
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if (request_mem_region(res.start, resource_size(&res),
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res.name) < 0)
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pr_err("Failed to request INTC register region\n");
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priv->reg[idx] = ioremap_nocache(res.start, resource_size(&res));
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if (!priv->reg[idx])
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panic("Failed to ioremap INTC register range");
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/* start up with everything masked before we hook the parent IRQ */
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__raw_writel(0, priv->reg[idx] + INTC_REG_ENABLE);
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priv->enable[idx] = 0;
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return IRQS_PER_WORD;
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}
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static int __init intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *domain;
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unsigned int parent_irq, n_irqs = 0;
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struct bcm3384_intc *priv;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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panic("Failed to allocate bcm3384_intc struct");
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spin_lock_init(&priv->lock);
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq)
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panic("Failed to get INTC IRQ");
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n_irqs += ioremap_one_pair(priv, node, 0);
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n_irqs += ioremap_one_pair(priv, node, 1);
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if (!n_irqs)
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panic("Failed to map INTC registers");
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priv->n_words = n_irqs / IRQS_PER_WORD;
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domain = irq_domain_add_linear(node, n_irqs, &irq_domain_ops, priv);
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if (!domain)
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panic("Failed to add irqdomain");
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irq_set_chained_handler(parent_irq, bcm3384_intc_irq_handler);
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irq_set_handler_data(parent_irq, domain);
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return 0;
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}
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static struct of_device_id of_irq_ids[] __initdata = {
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{ .compatible = "mti,cpu-interrupt-controller",
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.data = mips_cpu_irq_of_init },
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{ .compatible = "brcm,bcm3384-intc",
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.data = intc_of_init },
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{},
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};
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void __init arch_init_irq(void)
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{
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bmips_tp1_irqs = 0;
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of_irq_init(of_irq_ids);
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struct device_node *dn;
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/* Only the STB (bcm7038) controller supports SMP IRQ affinity */
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dn = of_find_compatible_node(NULL, NULL, "brcm,bcm7038-l1-intc");
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if (dn)
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of_node_put(dn);
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else
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bmips_tp1_irqs = 0;
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irqchip_init();
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}
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OF_DECLARE_2(irqchip, mips_cpu_intc, "mti,cpu-interrupt-controller",
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mips_cpu_irq_of_init);
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