drm/i915: Refine tracepoints
A lot of minor tweaks to fix the tracepoints, improve the outputting for ftrace, and to generally make the tracepoints useful again. It is a start and enough to begin identifying performance issues and gaps in our coverage. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
d9bc7e9f32
commit
db53a30261
11 changed files with 340 additions and 369 deletions
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@ -518,6 +518,8 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
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goto out;
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}
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trace_i915_gem_object_pread(obj, args->offset, args->size);
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ret = i915_gem_object_set_cpu_read_domain_range(obj,
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args->offset,
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args->size);
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@ -959,6 +961,8 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
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goto out;
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}
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trace_i915_gem_object_pwrite(obj, args->offset, args->size);
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/* We can only do the GTT pwrite on untiled buffers, as otherwise
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* it would end up going through the fenced access, and we'll get
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* different detiling behavior between reading and writing.
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@ -1175,6 +1179,8 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
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if (ret)
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goto out;
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trace_i915_gem_object_fault(obj, page_offset, true, write);
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/* Now bind it into the GTT if needed */
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if (!obj->map_and_fenceable) {
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ret = i915_gem_object_unbind(obj);
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@ -1668,9 +1674,8 @@ i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
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}
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static void
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i915_gem_process_flushing_list(struct drm_device *dev,
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uint32_t flush_domains,
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struct intel_ring_buffer *ring)
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i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
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uint32_t flush_domains)
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{
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struct drm_i915_gem_object *obj, *next;
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@ -1683,7 +1688,7 @@ i915_gem_process_flushing_list(struct drm_device *dev,
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obj->base.write_domain = 0;
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list_del_init(&obj->gpu_write_list);
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i915_gem_object_move_to_active(obj, ring,
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i915_gem_next_request_seqno(dev, ring));
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i915_gem_next_request_seqno(ring));
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trace_i915_gem_object_change_domain(obj,
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obj->base.read_domains,
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@ -1693,27 +1698,22 @@ i915_gem_process_flushing_list(struct drm_device *dev,
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}
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int
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i915_add_request(struct drm_device *dev,
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i915_add_request(struct intel_ring_buffer *ring,
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struct drm_file *file,
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struct drm_i915_gem_request *request,
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struct intel_ring_buffer *ring)
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struct drm_i915_gem_request *request)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_file_private *file_priv = NULL;
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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uint32_t seqno;
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int was_empty;
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int ret;
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BUG_ON(request == NULL);
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if (file != NULL)
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file_priv = file->driver_priv;
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ret = ring->add_request(ring, &seqno);
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if (ret)
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return ret;
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ring->outstanding_lazy_request = false;
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trace_i915_gem_request_add(ring, seqno);
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request->seqno = seqno;
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request->ring = ring;
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@ -1721,7 +1721,9 @@ i915_add_request(struct drm_device *dev,
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was_empty = list_empty(&ring->request_list);
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list_add_tail(&request->list, &ring->request_list);
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if (file_priv) {
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if (file) {
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struct drm_i915_file_private *file_priv = file->driver_priv;
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spin_lock(&file_priv->mm.lock);
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request->file_priv = file_priv;
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list_add_tail(&request->client_list,
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@ -1729,6 +1731,8 @@ i915_add_request(struct drm_device *dev,
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spin_unlock(&file_priv->mm.lock);
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}
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ring->outstanding_lazy_request = false;
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if (!dev_priv->mm.suspended) {
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mod_timer(&dev_priv->hangcheck_timer,
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jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
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@ -1845,18 +1849,15 @@ void i915_gem_reset(struct drm_device *dev)
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* This function clears the request list as sequence numbers are passed.
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*/
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static void
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i915_gem_retire_requests_ring(struct drm_device *dev,
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struct intel_ring_buffer *ring)
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i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t seqno;
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int i;
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if (!ring->status_page.page_addr ||
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list_empty(&ring->request_list))
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if (list_empty(&ring->request_list))
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return;
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WARN_ON(i915_verify_lists(dev));
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WARN_ON(i915_verify_lists(ring->dev));
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seqno = ring->get_seqno(ring);
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@ -1874,7 +1875,7 @@ i915_gem_retire_requests_ring(struct drm_device *dev,
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if (!i915_seqno_passed(seqno, request->seqno))
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break;
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trace_i915_gem_request_retire(dev, request->seqno);
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trace_i915_gem_request_retire(ring, request->seqno);
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list_del(&request->list);
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i915_gem_request_remove_from_client(request);
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@ -1900,13 +1901,13 @@ i915_gem_retire_requests_ring(struct drm_device *dev,
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i915_gem_object_move_to_inactive(obj);
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}
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if (unlikely (dev_priv->trace_irq_seqno &&
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i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
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if (unlikely(ring->trace_irq_seqno &&
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i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
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ring->irq_put(ring);
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dev_priv->trace_irq_seqno = 0;
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ring->trace_irq_seqno = 0;
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}
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WARN_ON(i915_verify_lists(dev));
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WARN_ON(i915_verify_lists(ring->dev));
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}
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void
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@ -1930,7 +1931,7 @@ i915_gem_retire_requests(struct drm_device *dev)
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}
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for (i = 0; i < I915_NUM_RINGS; i++)
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i915_gem_retire_requests_ring(dev, &dev_priv->ring[i]);
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i915_gem_retire_requests_ring(&dev_priv->ring[i]);
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}
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static void
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@ -1964,11 +1965,11 @@ i915_gem_retire_work_handler(struct work_struct *work)
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struct drm_i915_gem_request *request;
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int ret;
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ret = i915_gem_flush_ring(dev, ring, 0,
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I915_GEM_GPU_DOMAINS);
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ret = i915_gem_flush_ring(ring,
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0, I915_GEM_GPU_DOMAINS);
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request = kzalloc(sizeof(*request), GFP_KERNEL);
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if (ret || request == NULL ||
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i915_add_request(dev, NULL, request, ring))
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i915_add_request(ring, NULL, request))
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kfree(request);
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}
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@ -1981,11 +1982,16 @@ i915_gem_retire_work_handler(struct work_struct *work)
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mutex_unlock(&dev->struct_mutex);
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}
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/**
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* Waits for a sequence number to be signaled, and cleans up the
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* request and object lists appropriately for that event.
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*/
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int
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i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
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bool interruptible, struct intel_ring_buffer *ring)
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i915_wait_request(struct intel_ring_buffer *ring,
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uint32_t seqno,
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bool interruptible)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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u32 ier;
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int ret = 0;
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@ -2011,7 +2017,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
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if (request == NULL)
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return -ENOMEM;
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ret = i915_add_request(dev, NULL, request, ring);
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ret = i915_add_request(ring, NULL, request);
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if (ret) {
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kfree(request);
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return ret;
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@ -2021,18 +2027,18 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
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}
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if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
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if (HAS_PCH_SPLIT(dev))
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if (HAS_PCH_SPLIT(ring->dev))
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ier = I915_READ(DEIER) | I915_READ(GTIER);
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else
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ier = I915_READ(IER);
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if (!ier) {
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DRM_ERROR("something (likely vbetool) disabled "
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"interrupts, re-enabling\n");
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i915_driver_irq_preinstall(dev);
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i915_driver_irq_postinstall(dev);
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i915_driver_irq_preinstall(ring->dev);
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i915_driver_irq_postinstall(ring->dev);
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}
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trace_i915_gem_request_wait_begin(dev, seqno);
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trace_i915_gem_request_wait_begin(ring, seqno);
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ring->waiting_seqno = seqno;
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if (ring->irq_get(ring)) {
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@ -2052,7 +2058,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
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ret = -EBUSY;
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ring->waiting_seqno = 0;
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trace_i915_gem_request_wait_end(dev, seqno);
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trace_i915_gem_request_wait_end(ring, seqno);
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}
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if (atomic_read(&dev_priv->mm.wedged))
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ret = -EAGAIN;
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@ -2068,22 +2074,11 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
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* a separate wait queue to handle that.
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*/
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if (ret == 0)
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i915_gem_retire_requests_ring(dev, ring);
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i915_gem_retire_requests_ring(ring);
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return ret;
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}
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/**
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* Waits for a sequence number to be signaled, and cleans up the
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* request and object lists appropriately for that event.
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*/
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static int
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i915_wait_request(struct drm_device *dev, uint32_t seqno,
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struct intel_ring_buffer *ring)
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{
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return i915_do_wait_request(dev, seqno, 1, ring);
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}
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/**
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* Ensures that all rendering to the object has completed and the object is
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* safe to unbind from the GTT or access from the CPU.
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@ -2092,7 +2087,6 @@ int
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i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
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bool interruptible)
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{
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struct drm_device *dev = obj->base.dev;
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int ret;
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/* This function only exists to support waiting for existing rendering,
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@ -2104,10 +2098,9 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
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* it.
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*/
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if (obj->active) {
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ret = i915_do_wait_request(dev,
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obj->last_rendering_seqno,
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interruptible,
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obj->ring);
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ret = i915_wait_request(obj->ring,
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obj->last_rendering_seqno,
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interruptible);
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if (ret)
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return ret;
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}
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@ -2157,6 +2150,8 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
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if (ret == -ERESTARTSYS)
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return ret;
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trace_i915_gem_object_unbind(obj);
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i915_gem_gtt_unbind_object(obj);
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i915_gem_object_put_pages_gtt(obj);
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@ -2172,29 +2167,27 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
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if (i915_gem_object_is_purgeable(obj))
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i915_gem_object_truncate(obj);
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trace_i915_gem_object_unbind(obj);
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return ret;
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}
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int
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i915_gem_flush_ring(struct drm_device *dev,
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struct intel_ring_buffer *ring,
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i915_gem_flush_ring(struct intel_ring_buffer *ring,
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uint32_t invalidate_domains,
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uint32_t flush_domains)
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{
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int ret;
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trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
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ret = ring->flush(ring, invalidate_domains, flush_domains);
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if (ret)
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return ret;
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i915_gem_process_flushing_list(dev, flush_domains, ring);
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i915_gem_process_flushing_list(ring, flush_domains);
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return 0;
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}
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static int i915_ring_idle(struct drm_device *dev,
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struct intel_ring_buffer *ring)
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static int i915_ring_idle(struct intel_ring_buffer *ring)
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{
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int ret;
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@ -2202,15 +2195,15 @@ static int i915_ring_idle(struct drm_device *dev,
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return 0;
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if (!list_empty(&ring->gpu_write_list)) {
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ret = i915_gem_flush_ring(dev, ring,
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ret = i915_gem_flush_ring(ring,
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I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
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if (ret)
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return ret;
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}
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return i915_wait_request(dev,
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i915_gem_next_request_seqno(dev, ring),
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ring);
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return i915_wait_request(ring,
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i915_gem_next_request_seqno(ring),
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true);
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}
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int
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@ -2227,7 +2220,7 @@ i915_gpu_idle(struct drm_device *dev)
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/* Flush everything onto the inactive list. */
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for (i = 0; i < I915_NUM_RINGS; i++) {
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ret = i915_ring_idle(dev, &dev_priv->ring[i]);
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ret = i915_ring_idle(&dev_priv->ring[i]);
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if (ret)
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return ret;
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}
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@ -2418,8 +2411,7 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
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if (obj->fenced_gpu_access) {
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if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
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ret = i915_gem_flush_ring(obj->base.dev,
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obj->last_fenced_ring,
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ret = i915_gem_flush_ring(obj->last_fenced_ring,
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0, obj->base.write_domain);
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if (ret)
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return ret;
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@ -2431,10 +2423,10 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
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if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
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if (!ring_passed_seqno(obj->last_fenced_ring,
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obj->last_fenced_seqno)) {
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ret = i915_do_wait_request(obj->base.dev,
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obj->last_fenced_seqno,
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interruptible,
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obj->last_fenced_ring);
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ret = i915_wait_request(obj->last_fenced_ring,
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obj->last_fenced_seqno,
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interruptible);
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if (ret)
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return ret;
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}
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@ -2560,10 +2552,9 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
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if (reg->setup_seqno) {
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if (!ring_passed_seqno(obj->last_fenced_ring,
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reg->setup_seqno)) {
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ret = i915_do_wait_request(obj->base.dev,
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reg->setup_seqno,
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interruptible,
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obj->last_fenced_ring);
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ret = i915_wait_request(obj->last_fenced_ring,
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reg->setup_seqno,
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interruptible);
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if (ret)
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return ret;
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}
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@ -2580,7 +2571,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
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} else if (obj->tiling_changed) {
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if (obj->fenced_gpu_access) {
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if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
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ret = i915_gem_flush_ring(obj->base.dev, obj->ring,
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ret = i915_gem_flush_ring(obj->ring,
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0, obj->base.write_domain);
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if (ret)
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return ret;
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@ -2597,7 +2588,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
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if (obj->tiling_changed) {
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if (pipelined) {
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reg->setup_seqno =
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i915_gem_next_request_seqno(dev, pipelined);
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i915_gem_next_request_seqno(pipelined);
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obj->last_fenced_seqno = reg->setup_seqno;
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obj->last_fenced_ring = pipelined;
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}
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@ -2637,7 +2628,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
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old->fence_reg = I915_FENCE_REG_NONE;
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old->last_fenced_ring = pipelined;
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old->last_fenced_seqno =
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pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
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||||
pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
|
||||
|
||||
drm_gem_object_unreference(&old->base);
|
||||
} else if (obj->last_fenced_seqno == 0)
|
||||
|
|
@ -2649,7 +2640,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
|
|||
obj->last_fenced_ring = pipelined;
|
||||
|
||||
reg->setup_seqno =
|
||||
pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
|
||||
pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
|
||||
obj->last_fenced_seqno = reg->setup_seqno;
|
||||
|
||||
update:
|
||||
|
|
@ -2846,7 +2837,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
|
|||
|
||||
obj->map_and_fenceable = mappable && fenceable;
|
||||
|
||||
trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable);
|
||||
trace_i915_gem_object_bind(obj, map_and_fenceable);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -2869,13 +2860,11 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj)
|
|||
static int
|
||||
i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
|
||||
{
|
||||
struct drm_device *dev = obj->base.dev;
|
||||
|
||||
if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
|
||||
return 0;
|
||||
|
||||
/* Queue the GPU write cache flushing we need. */
|
||||
return i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
|
||||
return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
|
||||
}
|
||||
|
||||
/** Flushes the GTT write domain for the object if it's dirty. */
|
||||
|
|
@ -3024,8 +3013,7 @@ i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
|
|||
return 0;
|
||||
|
||||
if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
|
||||
ret = i915_gem_flush_ring(obj->base.dev, obj->ring,
|
||||
0, obj->base.write_domain);
|
||||
ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -3442,7 +3430,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
|
|||
* flush earlier is beneficial.
|
||||
*/
|
||||
if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
|
||||
ret = i915_gem_flush_ring(dev, obj->ring,
|
||||
ret = i915_gem_flush_ring(obj->ring,
|
||||
0, obj->base.write_domain);
|
||||
} else if (obj->ring->outstanding_lazy_request ==
|
||||
obj->last_rendering_seqno) {
|
||||
|
|
@ -3453,9 +3441,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
|
|||
*/
|
||||
request = kzalloc(sizeof(*request), GFP_KERNEL);
|
||||
if (request)
|
||||
ret = i915_add_request(dev,
|
||||
NULL, request,
|
||||
obj->ring);
|
||||
ret = i915_add_request(obj->ring, NULL,request);
|
||||
else
|
||||
ret = -ENOMEM;
|
||||
}
|
||||
|
|
@ -3465,7 +3451,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
|
|||
* are actually unmasked, and our working set ends up being
|
||||
* larger than required.
|
||||
*/
|
||||
i915_gem_retire_requests_ring(dev, obj->ring);
|
||||
i915_gem_retire_requests_ring(obj->ring);
|
||||
|
||||
args->busy = obj->active;
|
||||
}
|
||||
|
|
@ -3595,6 +3581,8 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
|
|||
kfree(obj->page_cpu_valid);
|
||||
kfree(obj->bit_17);
|
||||
kfree(obj);
|
||||
|
||||
trace_i915_gem_object_destroy(obj);
|
||||
}
|
||||
|
||||
void i915_gem_free_object(struct drm_gem_object *gem_obj)
|
||||
|
|
@ -3602,8 +3590,6 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
|
|||
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
|
||||
struct drm_device *dev = obj->base.dev;
|
||||
|
||||
trace_i915_gem_object_destroy(obj);
|
||||
|
||||
while (obj->pin_count > 0)
|
||||
i915_gem_object_unpin(obj);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue