dmaengine: k3: Split device_control
Split the device_control callback of the Hisilicon K3 DMA driver to make use of the newly introduced callbacks, that will eventually be used to retrieve slave capabilities. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Maxime Ripard
Vinod Koul
parent
701c1edbb4
commit
db08425ebd
1 changed files with 115 additions and 98 deletions
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@ -441,7 +441,7 @@ static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
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num = 0;
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if (!c->ccfg) {
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/* default is memtomem, without calling device_control */
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/* default is memtomem, without calling device_config */
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c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
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c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
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c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
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@ -523,112 +523,126 @@ static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
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return vchan_tx_prep(&c->vc, &ds->vd, flags);
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}
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static int k3_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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static int k3_dma_config(struct dma_chan *chan,
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struct dma_slave_config *cfg)
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{
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struct k3_dma_chan *c = to_k3_chan(chan);
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u32 maxburst = 0, val = 0;
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enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
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if (cfg == NULL)
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return -EINVAL;
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c->dir = cfg->direction;
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if (c->dir == DMA_DEV_TO_MEM) {
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c->ccfg = CX_CFG_DSTINCR;
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c->dev_addr = cfg->src_addr;
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maxburst = cfg->src_maxburst;
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width = cfg->src_addr_width;
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} else if (c->dir == DMA_MEM_TO_DEV) {
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c->ccfg = CX_CFG_SRCINCR;
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c->dev_addr = cfg->dst_addr;
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maxburst = cfg->dst_maxburst;
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width = cfg->dst_addr_width;
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}
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switch (width) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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case DMA_SLAVE_BUSWIDTH_8_BYTES:
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val = __ffs(width);
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break;
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default:
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val = 3;
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break;
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}
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c->ccfg |= (val << 12) | (val << 16);
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if ((maxburst == 0) || (maxburst > 16))
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val = 16;
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else
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val = maxburst - 1;
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c->ccfg |= (val << 20) | (val << 24);
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c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
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/* specific request line */
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c->ccfg |= c->vc.chan.chan_id << 4;
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return 0;
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}
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static int k3_dma_terminate_all(struct dma_chan *chan)
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{
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struct k3_dma_chan *c = to_k3_chan(chan);
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struct k3_dma_dev *d = to_k3_dma(chan->device);
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struct dma_slave_config *cfg = (void *)arg;
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struct k3_dma_phy *p = c->phy;
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unsigned long flags;
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u32 maxburst = 0, val = 0;
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enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
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LIST_HEAD(head);
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switch (cmd) {
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case DMA_SLAVE_CONFIG:
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if (cfg == NULL)
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return -EINVAL;
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c->dir = cfg->direction;
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if (c->dir == DMA_DEV_TO_MEM) {
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c->ccfg = CX_CFG_DSTINCR;
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c->dev_addr = cfg->src_addr;
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maxburst = cfg->src_maxburst;
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width = cfg->src_addr_width;
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} else if (c->dir == DMA_MEM_TO_DEV) {
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c->ccfg = CX_CFG_SRCINCR;
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c->dev_addr = cfg->dst_addr;
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maxburst = cfg->dst_maxburst;
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width = cfg->dst_addr_width;
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}
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switch (width) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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case DMA_SLAVE_BUSWIDTH_8_BYTES:
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val = __ffs(width);
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break;
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default:
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val = 3;
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break;
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}
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c->ccfg |= (val << 12) | (val << 16);
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dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
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if ((maxburst == 0) || (maxburst > 16))
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val = 16;
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else
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val = maxburst - 1;
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c->ccfg |= (val << 20) | (val << 24);
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c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
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/* Prevent this channel being scheduled */
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spin_lock(&d->lock);
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list_del_init(&c->node);
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spin_unlock(&d->lock);
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/* specific request line */
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c->ccfg |= c->vc.chan.chan_id << 4;
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break;
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case DMA_TERMINATE_ALL:
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dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
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/* Prevent this channel being scheduled */
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spin_lock(&d->lock);
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list_del_init(&c->node);
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spin_unlock(&d->lock);
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/* Clear the tx descriptor lists */
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spin_lock_irqsave(&c->vc.lock, flags);
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vchan_get_all_descriptors(&c->vc, &head);
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if (p) {
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/* vchan is assigned to a pchan - stop the channel */
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k3_dma_terminate_chan(p, d);
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c->phy = NULL;
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p->vchan = NULL;
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p->ds_run = p->ds_done = NULL;
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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vchan_dma_desc_free_list(&c->vc, &head);
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break;
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case DMA_PAUSE:
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dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
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if (c->status == DMA_IN_PROGRESS) {
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c->status = DMA_PAUSED;
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if (p) {
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k3_dma_pause_dma(p, false);
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} else {
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spin_lock(&d->lock);
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list_del_init(&c->node);
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spin_unlock(&d->lock);
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}
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}
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break;
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case DMA_RESUME:
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dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
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spin_lock_irqsave(&c->vc.lock, flags);
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if (c->status == DMA_PAUSED) {
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c->status = DMA_IN_PROGRESS;
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if (p) {
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k3_dma_pause_dma(p, true);
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} else if (!list_empty(&c->vc.desc_issued)) {
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spin_lock(&d->lock);
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list_add_tail(&c->node, &d->chan_pending);
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spin_unlock(&d->lock);
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}
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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break;
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default:
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return -ENXIO;
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/* Clear the tx descriptor lists */
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spin_lock_irqsave(&c->vc.lock, flags);
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vchan_get_all_descriptors(&c->vc, &head);
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if (p) {
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/* vchan is assigned to a pchan - stop the channel */
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k3_dma_terminate_chan(p, d);
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c->phy = NULL;
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p->vchan = NULL;
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p->ds_run = p->ds_done = NULL;
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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vchan_dma_desc_free_list(&c->vc, &head);
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return 0;
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}
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static int k3_dma_pause(struct dma_chan *chan)
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{
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struct k3_dma_chan *c = to_k3_chan(chan);
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struct k3_dma_dev *d = to_k3_dma(chan->device);
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struct k3_dma_phy *p = c->phy;
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dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
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if (c->status == DMA_IN_PROGRESS) {
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c->status = DMA_PAUSED;
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if (p) {
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k3_dma_pause_dma(p, false);
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} else {
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spin_lock(&d->lock);
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list_del_init(&c->node);
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spin_unlock(&d->lock);
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}
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}
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return 0;
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}
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static int k3_dma_resume(struct dma_chan *chan)
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{
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struct k3_dma_chan *c = to_k3_chan(chan);
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struct k3_dma_dev *d = to_k3_dma(chan->device);
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struct k3_dma_phy *p = c->phy;
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unsigned long flags;
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dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
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spin_lock_irqsave(&c->vc.lock, flags);
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if (c->status == DMA_PAUSED) {
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c->status = DMA_IN_PROGRESS;
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if (p) {
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k3_dma_pause_dma(p, true);
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} else if (!list_empty(&c->vc.desc_issued)) {
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spin_lock(&d->lock);
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list_add_tail(&c->node, &d->chan_pending);
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spin_unlock(&d->lock);
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}
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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return 0;
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}
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@ -720,7 +734,10 @@ static int k3_dma_probe(struct platform_device *op)
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d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
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d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
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d->slave.device_issue_pending = k3_dma_issue_pending;
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d->slave.device_control = k3_dma_control;
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d->slave.device_config = k3_dma_config;
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d->slave.device_pause = k3_dma_pause;
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d->slave.device_resume = k3_dma_resume;
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d->slave.device_terminate_all = k3_dma_terminate_all;
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d->slave.copy_align = DMA_ALIGN;
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/* init virtual channel */
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