Merge remote-tracking branch 'drm-upstream/drm-next' into drm-intel-next-queued
Backmerge drm-next so I can apply Maarten's drm/i915 atomic conversion patches. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
commit
ccb6662b7e
483 changed files with 12352 additions and 2888 deletions
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@ -786,6 +786,8 @@ struct drm_prime_handle {
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#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
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#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
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#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
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#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
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#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
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/**
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* Device specific ioctls should only be in their respective headers
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@ -558,4 +558,24 @@ struct drm_mode_atomic {
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__u64 user_data;
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};
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/**
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* Create a new 'blob' data property, copying length bytes from data pointer,
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* and returning new blob ID.
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*/
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struct drm_mode_create_blob {
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/** Pointer to data to copy. */
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__u64 data;
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/** Length of data to copy. */
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__u32 length;
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/** Return: new property ID. */
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__u32 blob_id;
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};
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/**
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* Destroy a user-created blob property.
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*/
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struct drm_mode_destroy_blob {
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__u32 blob_id;
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};
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#endif
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@ -1038,6 +1038,7 @@ struct drm_radeon_cs {
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#define RADEON_INFO_CURRENT_GPU_SCLK 0x22
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#define RADEON_INFO_CURRENT_GPU_MCLK 0x23
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#define RADEON_INFO_READ_REG 0x24
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#define RADEON_INFO_GPU_RESET_COUNTER 0x25
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struct drm_radeon_info {
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uint32_t request;
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@ -430,6 +430,7 @@ header-y += virtio_balloon.h
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header-y += virtio_blk.h
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header-y += virtio_config.h
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header-y += virtio_console.h
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header-y += virtio_gpu.h
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header-y += virtio_ids.h
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header-y += virtio_input.h
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header-y += virtio_net.h
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@ -128,6 +128,32 @@ struct kfd_ioctl_get_process_apertures_args {
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uint32_t pad;
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};
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#define MAX_ALLOWED_NUM_POINTS 100
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#define MAX_ALLOWED_AW_BUFF_SIZE 4096
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#define MAX_ALLOWED_WAC_BUFF_SIZE 128
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struct kfd_ioctl_dbg_register_args {
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uint32_t gpu_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_dbg_unregister_args {
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uint32_t gpu_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_dbg_address_watch_args {
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uint64_t content_ptr; /* a pointer to the actual content */
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uint32_t gpu_id; /* to KFD */
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uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
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};
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struct kfd_ioctl_dbg_wave_control_args {
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uint64_t content_ptr; /* a pointer to the actual content */
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uint32_t gpu_id; /* to KFD */
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uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
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};
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/* Matching HSA_EVENTTYPE */
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#define KFD_IOC_EVENT_SIGNAL 0
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#define KFD_IOC_EVENT_NODECHANGE 1
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@ -198,7 +224,8 @@ struct kfd_event_data {
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};
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struct kfd_ioctl_wait_events_args {
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uint64_t events_ptr; /* to KFD */
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uint64_t events_ptr; /* pointed to struct
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kfd_event_data array, to KFD */
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uint32_t num_events; /* to KFD */
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uint32_t wait_for_all; /* to KFD */
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uint32_t timeout; /* to KFD */
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@ -247,7 +274,19 @@ struct kfd_ioctl_wait_events_args {
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#define AMDKFD_IOC_WAIT_EVENTS \
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AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
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#define AMDKFD_IOC_DBG_REGISTER \
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AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
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#define AMDKFD_IOC_DBG_UNREGISTER \
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AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
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#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
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AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
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#define AMDKFD_IOC_DBG_WAVE_CONTROL \
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AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
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#define AMDKFD_COMMAND_START 0x01
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#define AMDKFD_COMMAND_END 0x0D
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#define AMDKFD_COMMAND_END 0x11
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#endif
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@ -42,6 +42,9 @@ enum tcp_conntrack {
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/* The field td_maxack has been set */
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#define IP_CT_TCP_FLAG_MAXACK_SET 0x20
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/* Marks possibility for expected RFC5961 challenge ACK */
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#define IP_CT_EXP_CHALLENGE_ACK 0x40
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struct nf_ct_tcp_flags {
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__u8 flags;
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__u8 mask;
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@ -337,7 +337,7 @@ struct rtnexthop {
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#define RTNH_F_DEAD 1 /* Nexthop is dead (used by multipath) */
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#define RTNH_F_PERVASIVE 2 /* Do recursive gateway lookup */
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#define RTNH_F_ONLINK 4 /* Gateway is forced on link */
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#define RTNH_F_EXTERNAL 8 /* Route installed externally */
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#define RTNH_F_OFFLOAD 8 /* offloaded route */
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/* Macros to handle hexthops */
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204
include/uapi/linux/virtio_gpu.h
Normal file
204
include/uapi/linux/virtio_gpu.h
Normal file
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@ -0,0 +1,204 @@
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/*
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* Virtio GPU Device
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*
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* Copyright Red Hat, Inc. 2013-2014
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*
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* Authors:
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* Dave Airlie <airlied@redhat.com>
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* Gerd Hoffmann <kraxel@redhat.com>
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*
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* This header is BSD licensed so anyone can use the definitions
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* to implement compatible drivers/servers:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of IBM nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef VIRTIO_GPU_HW_H
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#define VIRTIO_GPU_HW_H
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enum virtio_gpu_ctrl_type {
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VIRTIO_GPU_UNDEFINED = 0,
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/* 2d commands */
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VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
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VIRTIO_GPU_CMD_RESOURCE_UNREF,
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VIRTIO_GPU_CMD_SET_SCANOUT,
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VIRTIO_GPU_CMD_RESOURCE_FLUSH,
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VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
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VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
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VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
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/* cursor commands */
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VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
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VIRTIO_GPU_CMD_MOVE_CURSOR,
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/* success responses */
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VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
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VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
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/* error responses */
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VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
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VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
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VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
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};
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#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
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struct virtio_gpu_ctrl_hdr {
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__le32 type;
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__le32 flags;
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__le64 fence_id;
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__le32 ctx_id;
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__le32 padding;
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};
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/* data passed in the cursor vq */
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struct virtio_gpu_cursor_pos {
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__le32 scanout_id;
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__le32 x;
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__le32 y;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
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struct virtio_gpu_update_cursor {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_cursor_pos pos; /* update & move */
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__le32 resource_id; /* update only */
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__le32 hot_x; /* update only */
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__le32 hot_y; /* update only */
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__le32 padding;
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};
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/* data passed in the control vq, 2d related */
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struct virtio_gpu_rect {
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__le32 x;
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__le32 y;
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__le32 width;
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__le32 height;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
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struct virtio_gpu_resource_unref {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
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struct virtio_gpu_resource_create_2d {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 format;
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__le32 width;
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__le32 height;
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};
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/* VIRTIO_GPU_CMD_SET_SCANOUT */
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struct virtio_gpu_set_scanout {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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__le32 scanout_id;
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__le32 resource_id;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
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struct virtio_gpu_resource_flush {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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__le32 resource_id;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
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struct virtio_gpu_transfer_to_host_2d {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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__le64 offset;
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__le32 resource_id;
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__le32 padding;
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};
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struct virtio_gpu_mem_entry {
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__le64 addr;
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__le32 length;
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__le32 padding;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
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struct virtio_gpu_resource_attach_backing {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 nr_entries;
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};
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/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
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struct virtio_gpu_resource_detach_backing {
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struct virtio_gpu_ctrl_hdr hdr;
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__le32 resource_id;
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__le32 padding;
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};
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/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
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#define VIRTIO_GPU_MAX_SCANOUTS 16
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struct virtio_gpu_resp_display_info {
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_display_one {
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struct virtio_gpu_rect r;
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__le32 enabled;
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__le32 flags;
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} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
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};
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#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
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struct virtio_gpu_config {
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__u32 events_read;
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__u32 events_clear;
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__u32 num_scanouts;
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__u32 reserved;
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};
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/* simple formats for fbcon/X use */
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enum virtio_gpu_formats {
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VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
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VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
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VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
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VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
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VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
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VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
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VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
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VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
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};
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#endif
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@ -39,6 +39,7 @@
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#define VIRTIO_ID_9P 9 /* 9p virtio console */
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#define VIRTIO_ID_RPROC_SERIAL 11 /* virtio remoteproc serial link */
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#define VIRTIO_ID_CAIF 12 /* Virtio caif */
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#define VIRTIO_ID_GPU 16 /* virtio GPU */
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#define VIRTIO_ID_INPUT 18 /* virtio input */
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#endif /* _LINUX_VIRTIO_IDS_H */
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