spi: Updates for v3.15
A busy release for both cleanups and new drivers this time along with
further factoring out of replicated code into the core:
- Provide support in the core for DMA mapping transfers - essentially
all drivers weren't implementing this properly, now there's no
excuse.
- Dual and quad mode support for spidev.
- Fix handling of cs_change in the generic implementation.
- Remove the S3C_DMA code from the s3c64xx driver now that all the
platforms using it have been converted to dmaengine.
- Lots of improvements to the Renesas SPI controllers.
- Drivers for Allwinner A10 and A31, Qualcomm QUP and Xylinx xtfpga.
- Removal of the bitrotted ti-ssp driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJTOUttAAoJELSic+t+oim9NqMQAI3zR6K5e7o/GJhxWMOBDkdo
hN0ZSt6NEYGHQqXZ0kR0Azj7I3PO/Bj0US2gYx1myfggV/++rZwgGI97fsF9dBoN
IbOm+xBx5nmMkr0/oxZD/ETbM74iVm7xM274OKHLD1spiozqwGNV4voEvt/JVQ8W
ux+8SFa8HC0GoDqm6Ha51RstiBGFpuvKYUpeRmSEvsRl9DpyHhnQeZg/gwiQm/ON
n74twLTXTIBO7oVxTpffsZgRPfvZtIcNmwwL+gyYBrjb5DZ1+qCTPGYx0/R18wfr
NrXIYv8Ka6qbDiwWhmf6m5qrNsYNq95t2J6ulxor1LVcAIZODBpcEfdQ51fwYd3f
+xZuCTzPRZ2w8Mha2II6LvOjk0640MBa/nQnOEup8dTWX0jARPKnKcjb84tuhlna
ZGolHABLUhzZIAQjkZjbVSw0HL6lAQ/mk8sZevcCmB2zCln+HneeFCVCEWjy+i2I
zejhFJMT3/MqLqZNav+MzkkYB1aW3q/RQz7OwzwPK7Rlw0IRwd64c0D9r9Qj2/Gl
uWVOnLmgDwKgeq7464kA4ELPTW0i9gG7SIQe18xzkL2SY9wzQN0S1ERx3aDCCAw2
lyuh/Cdz7nnCyDBmuqNUfvp8XAX1d0d12vTbHcW1VHMw68fE4OBVNxn4jUXHZt5O
OmOoox/sn/1I+Ce30C70
=qoZY
-----END PGP SIGNATURE-----
Merge tag 'spi-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi Updates from Mark Brown:
"A busy release for both cleanups and new drivers this time along with
further factoring out of replicated code into the core:
- Provide support in the core for DMA mapping transfers - essentially
all drivers weren't implementing this properly, now there's no
excuse.
- Dual and quad mode support for spidev.
- Fix handling of cs_change in the generic implementation.
- Remove the S3C_DMA code from the s3c64xx driver now that all the
platforms using it have been converted to dmaengine.
- Lots of improvements to the Renesas SPI controllers.
- Drivers for Allwinner A10 and A31, Qualcomm QUP and Xylinx xtfpga.
- Removal of the bitrotted ti-ssp driver"
* tag 'spi-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (199 commits)
spi: Fix handling of cs_change in core implementation
spi: bitbang: Make spi_bitbang_stop() return void
spi: mpc52xx: Convert to use bits_per_word_mask
spi: omap-100k: Fix memory leak
spi: dw: Don't call kfree for memory allocated by devm_kzalloc
spi: fsl-dspi: Fix memory leak
spi: omap-uwire: add missing iounmap
spi: clps711x: Convert to use master->max_speed_hz
spi: clps711x: Enable driver compilation with COMPILE_TEST
spi: omap-uwire: Remove full duplex check
spi: Do not require a completion
spi: topcliff-pch: Transform noisy message to dev_vdbg
spi: coldfire-qspi: Simplify the code to set register bits for transfer speed
spi: bcm63xx: Remove unused define for PFX
spi: efm32: use $vendor,$device scheme for compatible string
spi: clps711x: Remove <mach/hardware.h> dependency
spi: topcliff-pch: Properly unregister platform devices on probe() error paths
spi: fsl-espi: Remove unused bits_per_word variable in fsl_espi_bufs
spi: altera: Remove the code to get unused platform_data
spi: fsl-lib: Fix memory leak of pinfo
...
This commit is contained in:
commit
c12ac9f98e
84 changed files with 4010 additions and 2266 deletions
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@ -42,6 +42,10 @@
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#define SPI_LOOP 0x20
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#define SPI_NO_CS 0x40
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#define SPI_READY 0x80
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#define SPI_TX_DUAL 0x100
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#define SPI_TX_QUAD 0x200
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#define SPI_RX_DUAL 0x400
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#define SPI_RX_QUAD 0x800
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/*---------------------------------------------------------------------------*/
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@ -92,7 +96,9 @@ struct spi_ioc_transfer {
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__u16 delay_usecs;
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__u8 bits_per_word;
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__u8 cs_change;
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__u32 pad;
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__u8 tx_nbits;
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__u8 rx_nbits;
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__u16 pad;
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/* If the contents of 'struct spi_ioc_transfer' ever change
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* incompatibly, then the ioctl number (currently 0) must change;
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@ -110,7 +116,7 @@ struct spi_ioc_transfer {
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#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
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/* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) */
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/* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) (limited to 8 bits) */
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#define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8)
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#define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8)
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@ -126,6 +132,10 @@ struct spi_ioc_transfer {
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#define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32)
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#define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32)
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/* Read / Write of the SPI mode field */
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#define SPI_IOC_RD_MODE32 _IOR(SPI_IOC_MAGIC, 5, __u32)
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#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32)
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#endif /* SPIDEV_H */
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