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[media] tm6000: Rework standard register tables

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This commit uses sentinel entries to terminate the TV standard register
tables instead of hard-coding their size, allowing further entries to be
added more easily. It is also more space-efficient if the tables have a
varying number of entries.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Thierry Reding 2011-08-04 04:14:09 -03:00 • committed by Mauro Carvalho Chehab
parent 873545820a
commit c0fa65ff9e
1 changed files with 289 additions and 311 deletions
Download patch file Download diff file Expand all files Collapse all files

154
drivers/staging/tm6000/tm6000-stds.c
View file

@ -35,13 +35,10 @@ struct tm6000_reg_settings {
struct tm6000_std_settings {
v4l2_std_id id;
struct tm6000_reg_settings common[27];
struct tm6000_reg_settings *common;
};
static struct tm6000_std_settings composite_stds[] = {
{
.id = V4L2_STD_PAL_M,
.common = {
static struct tm6000_reg_settings composite_pal_m[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
@ -62,16 +59,14 @@ static struct tm6000_std_settings composite_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
{ TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
}, {
.id = V4L2_STD_PAL_Nc,
.common = {
{ 0, 0, 0 }
};
static struct tm6000_reg_settings composite_pal_nc[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
@ -92,16 +87,14 @@ static struct tm6000_std_settings composite_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
{ TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
}, {
.id = V4L2_STD_PAL,
.common = {
{ 0, 0, 0 }
};
static struct tm6000_reg_settings composite_pal[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
@ -122,16 +115,14 @@ static struct tm6000_std_settings composite_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
{ TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
}, {
.id = V4L2_STD_SECAM,
.common = {
{ 0, 0, 0 }
};
static struct tm6000_reg_settings composite_secam[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
@ -152,15 +143,13 @@ static struct tm6000_std_settings composite_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18 },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xff },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
}, {
.id = V4L2_STD_NTSC,
.common = {
{ 0, 0, 0 }
};
static struct tm6000_reg_settings composite_ntsc[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f },
@ -181,20 +170,22 @@ static struct tm6000_std_settings composite_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
{ TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
},
{ 0, 0, 0 }
};
static struct tm6000_std_settings svideo_stds[] = {
{
.id = V4L2_STD_PAL_M,
.common = {
static struct tm6000_std_settings composite_stds[] = {
{ .id = V4L2_STD_PAL_M, .common = composite_pal_m, },
{ .id = V4L2_STD_PAL_Nc, .common = composite_pal_nc, },
{ .id = V4L2_STD_PAL, .common = composite_pal, },
{ .id = V4L2_STD_SECAM, .common = composite_secam, },
{ .id = V4L2_STD_NTSC, .common = composite_ntsc, },
};
static struct tm6000_reg_settings svideo_pal_m[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x05 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
@ -215,16 +206,14 @@ static struct tm6000_std_settings svideo_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
{ TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
}, {
.id = V4L2_STD_PAL_Nc,
.common = {
{ 0, 0, 0 }
};
static struct tm6000_reg_settings svideo_pal_nc[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x37 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
@ -245,16 +234,14 @@ static struct tm6000_std_settings svideo_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
{ TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
}, {
.id = V4L2_STD_PAL,
.common = {
{ 0, 0, 0 }
};
static struct tm6000_reg_settings svideo_pal[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x33 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
@ -275,16 +262,14 @@ static struct tm6000_std_settings svideo_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
{ TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
}, {
.id = V4L2_STD_SECAM,
.common = {
{ 0, 0, 0 }
};
static struct tm6000_reg_settings svideo_secam[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
@ -305,15 +290,13 @@ static struct tm6000_std_settings svideo_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18 },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xff },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
}, {
.id = V4L2_STD_NTSC,
.common = {
{ 0, 0, 0 }
};
static struct tm6000_reg_settings svideo_ntsc[] = {
{ TM6010_REQ07_R3F_RESET, 0x01 },
{ TM6010_REQ07_R00_VIDEO_CONTROL0, 0x01 },
{ TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f },
@ -335,16 +318,20 @@ static struct tm6000_std_settings svideo_stds[] = {
{ TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
{ TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
{ TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
{TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
{ TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
{ TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd },
{ TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
{ TM6010_REQ07_R3F_RESET, 0x00 },
{0, 0, 0},
},
},
{ 0, 0, 0 }
};
static struct tm6000_std_settings svideo_stds[] = {
{ .id = V4L2_STD_PAL_M, .common = svideo_pal_m, },
{ .id = V4L2_STD_PAL_Nc, .common = svideo_pal_nc, },
{ .id = V4L2_STD_PAL, .common = svideo_pal, },
{ .id = V4L2_STD_SECAM, .common = svideo_secam, },
{ .id = V4L2_STD_NTSC, .common = svideo_ntsc, },
};
static int tm6000_set_audio_std(struct tm6000_core *dev)
{
@ -501,16 +488,12 @@ void tm6000_get_std_res(struct tm6000_core *dev)
dev->width = 720;
}
static int tm6000_load_std(struct tm6000_core *dev,
struct tm6000_reg_settings *set, int max_size)
static int tm6000_load_std(struct tm6000_core *dev, struct tm6000_reg_settings *set)
{
int i, rc;
/* Load board's initialization table */
for (i = 0; max_size; i++) {
if (!set[i].req)
return 0;
for (i = 0; set[i].req; i++) {
rc = tm6000_set_reg(dev, set[i].req, set[i].reg, set[i].value);
if (rc < 0) {
printk(KERN_ERR "Error %i while setting "
@ -645,9 +628,7 @@ int tm6000_set_standard(struct tm6000_core *dev)
if (input->type == TM6000_INPUT_SVIDEO) {
for (i = 0; i < ARRAY_SIZE(svideo_stds); i++) {
if (dev->norm & svideo_stds[i].id) {
rc = tm6000_load_std(dev, svideo_stds[i].common,
sizeof(svideo_stds[i].
common));
rc = tm6000_load_std(dev, svideo_stds[i].common);
goto ret;
}
}
@ -655,10 +636,7 @@ int tm6000_set_standard(struct tm6000_core *dev)
} else {
for (i = 0; i < ARRAY_SIZE(composite_stds); i++) {
if (dev->norm & composite_stds[i].id) {
rc = tm6000_load_std(dev,
composite_stds[i].common,
sizeof(composite_stds[i].
common));
rc = tm6000_load_std(dev, composite_stds[i].common);
goto ret;
}
}