ARM: S5P6440: Add IRQ support
This patch adds IRQ support for S5P6440 CPU. Signed-off-by: Adityapratap Sharma <aditya.ps@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Kukjin Kim
Ben Dooks
parent
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commit
b7db51be43
4 changed files with 286 additions and 0 deletions
111
arch/arm/mach-s5p6440/include/mach/irqs.h
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arch/arm/mach-s5p6440/include/mach/irqs.h
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/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h
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*
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* Copyright 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P6440 - IRQ definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_S5P_IRQS_H
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#define __ASM_ARCH_S5P_IRQS_H __FILE__
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#include <plat/irqs.h>
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/* VIC0 */
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#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
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#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
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#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
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#define IRQ_IIC1 S5P_IRQ_VIC0(5)
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#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
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#define IRQ_GPS S5P_IRQ_VIC0(7)
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#define IRQ_POST0 S5P_IRQ_VIC0(9)
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#define IRQ_2D S5P_IRQ_VIC0(11)
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#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
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#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
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#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
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#define IRQ_WDT S5P_IRQ_VIC0(26)
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#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
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#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
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#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
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#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
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#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
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/* VIC1 */
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#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
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#define IRQ_PCM0 S5P_IRQ_VIC1(2)
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#define IRQ_UART0 S5P_IRQ_VIC1(5)
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#define IRQ_UART1 S5P_IRQ_VIC1(6)
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#define IRQ_UART2 S5P_IRQ_VIC1(7)
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#define IRQ_UART3 S5P_IRQ_VIC1(8)
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#define IRQ_DMA0 S5P_IRQ_VIC1(9)
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#define IRQ_NFC S5P_IRQ_VIC1(13)
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#define IRQ_SPI0 S5P_IRQ_VIC1(16)
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#define IRQ_SPI1 S5P_IRQ_VIC1(17)
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#define IRQ_IIC S5P_IRQ_VIC1(18)
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#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
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#define IRQ_FIMGVG S5P_IRQ_VIC1(20)
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#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
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#define IRQ_PMUIRQ S5P_IRQ_VIC1(23)
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#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
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#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
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#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
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#define IRQ_OTG S5P_IRQ_VIC1(26)
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#define IRQ_DSI S5P_IRQ_VIC1(27)
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#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
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#define IRQ_TSI S5P_IRQ_VIC1(29)
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#define IRQ_PENDN S5P_IRQ_VIC1(30)
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#define IRQ_TC IRQ_PENDN
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#define IRQ_ADC S5P_IRQ_VIC1(31)
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/*
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* Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
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* them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
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* after the pair of VICs.
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*/
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#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
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#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
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#define IRQ_EINT(x) S5P_EINT(x)
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/*
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* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
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* that they are sourced from the GPIO pins but with a different scheme for
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* priority and source indication.
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*
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* The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
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* interrupts, but for historical reasons they are kept apart from these
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* next interrupts.
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*
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* Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
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* machine specific support files.
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*/
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/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
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#define IRQ_EINT_GROUP1_NR (15)
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#define IRQ_EINT_GROUP2_NR (8)
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#define IRQ_EINT_GROUP5_NR (7)
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#define IRQ_EINT_GROUP6_NR (10)
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/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
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#define IRQ_EINT_GROUP8_NR (11)
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#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
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#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
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#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
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#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
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#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
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#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
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#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
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/* Set the default NR_IRQS */
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#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
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#endif /* __ASM_ARCH_S5P_IRQS_H */
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19
arch/arm/mach-s5p6440/include/mach/regs-irq.h
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arch/arm/mach-s5p6440/include/mach/regs-irq.h
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/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P6440 - IRQ register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_IRQ_H
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#define __ASM_ARCH_REGS_IRQ_H __FILE__
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#include <asm/hardware/vic.h>
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#include <mach/map.h>
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#endif /* __ASM_ARCH_REGS_IRQ_H */
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arch/arm/plat-s5p/include/plat/irqs.h
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arch/arm/plat-s5p/include/plat/irqs.h
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/* linux/arch/arm/plat-s5p/include/plat/irqs.h
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P Common IRQ support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_S5P_IRQS_H
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#define __ASM_PLAT_S5P_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*
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* note, since we're using the VICs, our start must be a
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* mulitple of 32 to allow the common code to work
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*/
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#define S5P_IRQ_OFFSET (32)
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#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
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#define S5P_VIC0_BASE S5P_IRQ(0)
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#define S5P_VIC1_BASE S5P_IRQ(32)
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#define IRQ_VIC0_BASE S5P_VIC0_BASE
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#define IRQ_VIC1_BASE S5P_VIC1_BASE
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/* UART interrupts, each UART has 4 intterupts per channel so
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* use the space between the ISA and S3C main interrupts. Note, these
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* are not in the same order as the S3C24XX series! */
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#define IRQ_S5P_UART_BASE0 (16)
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#define IRQ_S5P_UART_BASE1 (20)
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#define IRQ_S5P_UART_BASE2 (24)
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#define IRQ_S5P_UART_BASE3 (28)
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#define UART_IRQ_RXD (0)
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#define UART_IRQ_ERR (1)
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#define UART_IRQ_TXD (2)
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#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR)
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#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR)
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#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR)
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#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR)
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/* S3C compatibilty defines */
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#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0
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#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1
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#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2
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#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3
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/* VIC based IRQs */
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#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
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#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
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#define S5P_TIMER_IRQ(x) S5P_IRQ(64 + (x))
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#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
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#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
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#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
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#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
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#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
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#endif /* __ASM_PLAT_S5P_IRQS_H */
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arch/arm/plat-s5p/irq.c
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arch/arm/plat-s5p/irq.c
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/* arch/arm/plat-s5p/irq.c
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P - Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/vic.h>
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#include <linux/serial_core.h>
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#include <mach/map.h>
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#include <plat/regs-timer.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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#include <plat/irq-vic-timer.h>
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#include <plat/irq-uart.h>
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#define VIC_VAADDR(no) (S5P_VA_VIC0 + ((no)*0x10000))
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#define VIC_BASE(no) (S5P_VIC0_BASE + ((no)*32))
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/*
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* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
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* are consecutive when looking up the interrupt in the demux routines.
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*/
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static struct s3c_uart_irq uart_irqs[] = {
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[0] = {
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.regs = S5P_VA_UART0,
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.base_irq = IRQ_S5P_UART_BASE0,
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.parent_irq = IRQ_UART0,
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},
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[1] = {
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.regs = S5P_VA_UART1,
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.base_irq = IRQ_S5P_UART_BASE1,
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.parent_irq = IRQ_UART1,
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},
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[2] = {
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.regs = S5P_VA_UART2,
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.base_irq = IRQ_S5P_UART_BASE2,
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.parent_irq = IRQ_UART2,
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},
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[3] = {
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.regs = S5P_VA_UART3,
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.base_irq = IRQ_S5P_UART_BASE3,
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.parent_irq = IRQ_UART3,
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},
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};
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void __init s5p_init_irq(u32 *vic, u32 num_vic)
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{
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int irq;
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/* initialize the VICs */
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for (irq = 0; irq < num_vic; irq++)
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vic_init(VIC_VAADDR(irq), VIC_BASE(irq), vic[irq], 0);
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s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
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s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
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s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
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s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
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s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
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s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
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}
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