ARM: at91/PMC: make register base soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Reviewed-by: Ryan Mallon <rmallon@gmail.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
Nicolas Ferre
parent
940192e3c6
commit
b55149529d
14 changed files with 104 additions and 95 deletions
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@ -295,7 +295,7 @@ static void at91rm9200_idle(void)
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* Disable the processor clock. The processor will be automatically
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* re-enabled by an interrupt or by a reset.
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*/
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at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
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at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
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}
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static void at91rm9200_restart(char mode, const char *cmd)
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@ -33,6 +33,7 @@
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#include "clock.h"
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#include "generic.h"
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void __iomem *at91_pmc_base;
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/*
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* There's a lot more which can be done with clocks, including cpufreq
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@ -125,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
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value = 0;
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// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
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at91_sys_write(AT91_CKGR_PLLBR, value);
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at91_pmc_write(AT91_CKGR_PLLBR, value);
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do {
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cpu_relax();
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} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
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} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
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}
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static struct clk pllb = {
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@ -144,24 +145,24 @@ static struct clk pllb = {
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static void pmc_sys_mode(struct clk *clk, int is_on)
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{
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if (is_on)
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at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
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at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
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else
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at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
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at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
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}
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static void pmc_uckr_mode(struct clk *clk, int is_on)
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{
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unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
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unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
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if (is_on) {
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is_on = AT91_PMC_LOCKU;
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at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
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at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
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} else
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at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
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at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
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do {
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cpu_relax();
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} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
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} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
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}
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/* USB function clocks (PLLB must be 48 MHz) */
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@ -197,9 +198,9 @@ struct clk mck = {
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static void pmc_periph_mode(struct clk *clk, int is_on)
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{
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if (is_on)
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at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
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at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
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else
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at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
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at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
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}
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static struct clk __init *at91_css_to_clk(unsigned long css)
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@ -359,10 +360,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
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if (actual && actual <= rate) {
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u32 pckr;
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pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
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pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
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pckr &= css_mask; /* keep clock selection */
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pckr |= prescale << prescale_offset;
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at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
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at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
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clk->rate_hz = actual;
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break;
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}
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@ -396,7 +397,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
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clk->rate_hz = parent->rate_hz;
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clk->parent = parent;
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at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
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at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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@ -415,7 +416,7 @@ static void __init init_programmable_clock(struct clk *clk)
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else
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css_mask = AT91_PMC_CSS;
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pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
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pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
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parent = at91_css_to_clk(pckr & css_mask);
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clk->parent = parent;
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clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
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@ -432,23 +433,23 @@ static int at91_clk_show(struct seq_file *s, void *unused)
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u32 scsr, pcsr, uckr = 0, sr;
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struct clk *clk;
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scsr = at91_sys_read(AT91_PMC_SCSR);
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pcsr = at91_sys_read(AT91_PMC_PCSR);
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sr = at91_sys_read(AT91_PMC_SR);
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scsr = at91_pmc_read(AT91_PMC_SCSR);
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pcsr = at91_pmc_read(AT91_PMC_PCSR);
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sr = at91_pmc_read(AT91_PMC_SR);
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seq_printf(s, "SCSR = %8x\n", scsr);
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seq_printf(s, "PCSR = %8x\n", pcsr);
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seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
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seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
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seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
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seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
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seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
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seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
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if (cpu_has_pllb())
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seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
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seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
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if (cpu_has_utmi()) {
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uckr = at91_sys_read(AT91_CKGR_UCKR);
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uckr = at91_pmc_read(AT91_CKGR_UCKR);
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seq_printf(s, "UCKR = %8x\n", uckr);
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}
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seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
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seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
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if (cpu_has_upll())
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seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB));
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seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
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seq_printf(s, "SR = %8x\n", sr);
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seq_printf(s, "\n");
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@ -637,14 +638,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
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if (cpu_is_at91rm9200()) {
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uhpck.pmc_mask = AT91RM9200_PMC_UHP;
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udpck.pmc_mask = AT91RM9200_PMC_UDP;
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at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
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at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
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} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
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cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
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cpu_is_at91sam9g10()) {
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uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
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udpck.pmc_mask = AT91SAM926x_PMC_UDP;
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}
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at91_sys_write(AT91_CKGR_PLLBR, 0);
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at91_pmc_write(AT91_CKGR_PLLBR, 0);
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udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
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@ -661,13 +662,13 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
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/* Setup divider by 10 to reach 48 MHz */
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usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
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at91_sys_write(AT91_PMC_USB, usbr);
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at91_pmc_write(AT91_PMC_USB, usbr);
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/* Now set uhpck values */
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uhpck.parent = &utmi_clk;
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uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
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uhpck.rate_hz = utmi_clk.rate_hz;
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uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
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uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
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}
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int __init at91_clock_init(unsigned long main_clock)
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@ -676,6 +677,10 @@ int __init at91_clock_init(unsigned long main_clock)
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int i;
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int pll_overclock = false;
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at91_pmc_base = ioremap(AT91_PMC, 256);
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if (!at91_pmc_base)
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panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
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/*
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* When the bootloader initialized the main oscillator correctly,
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* there's no problem using the cycle counter. But if it didn't,
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@ -684,14 +689,14 @@ int __init at91_clock_init(unsigned long main_clock)
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*/
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if (!main_clock) {
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do {
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tmp = at91_sys_read(AT91_CKGR_MCFR);
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tmp = at91_pmc_read(AT91_CKGR_MCFR);
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} while (!(tmp & AT91_PMC_MAINRDY));
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main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
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}
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main_clk.rate_hz = main_clock;
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/* report if PLLA is more than mildly overclocked */
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plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
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plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
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if (cpu_has_300M_plla()) {
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if (plla.rate_hz > 300000000)
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pll_overclock = true;
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@ -706,7 +711,7 @@ int __init at91_clock_init(unsigned long main_clock)
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pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
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if (cpu_has_plladiv2()) {
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mckr = at91_sys_read(AT91_PMC_MCKR);
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mckr = at91_pmc_read(AT91_PMC_MCKR);
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plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
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}
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@ -746,7 +751,7 @@ int __init at91_clock_init(unsigned long main_clock)
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* MCK and CPU derive from one of those primary clocks.
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* For now, assume this parentage won't change.
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*/
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mckr = at91_sys_read(AT91_PMC_MCKR);
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mckr = at91_pmc_read(AT91_PMC_MCKR);
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mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
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freq = mck.parent->rate_hz;
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freq /= pmc_prescaler_divider(mckr); /* prescale */
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@ -819,8 +824,8 @@ static int __init at91_clock_reset(void)
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pr_debug("Clocks: disable unused %s\n", clk->name);
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}
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at91_sys_write(AT91_PMC_PCDR, pcdr);
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at91_sys_write(AT91_PMC_SCDR, scdr);
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at91_pmc_write(AT91_PMC_PCDR, pcdr);
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at91_pmc_write(AT91_PMC_SCDR, scdr);
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return 0;
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}
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@ -828,6 +833,6 @@ late_initcall(at91_clock_reset);
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void at91sam9_idle(void)
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{
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at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
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at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
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cpu_do_idle();
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}
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@ -16,10 +16,22 @@
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#ifndef AT91_PMC_H
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#define AT91_PMC_H
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#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
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#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
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#ifndef __ASSEMBLY__
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extern void __iomem *at91_pmc_base;
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#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
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#define at91_pmc_read(field) \
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__raw_readl(at91_pmc_base + field)
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#define at91_pmc_write(field, value) \
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__raw_writel(value, at91_pmc_base + field)
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#else
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.extern at91_aic_base
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#endif
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#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
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#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
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#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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@ -34,17 +46,17 @@
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#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
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#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
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#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
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#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
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#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
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#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
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#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
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#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
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#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9] */
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#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
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#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
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#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
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#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
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#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
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#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
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@ -53,12 +65,12 @@
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#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
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#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
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#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
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#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
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#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
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#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
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#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
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#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
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#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
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#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
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#define AT91_PMC_DIV (0xff << 0) /* Divider */
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#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
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#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
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@ -69,7 +81,7 @@
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#define AT91_PMC_USBDIV_4 (2 << 28)
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#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
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#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
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#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
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#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
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#define AT91_PMC_CSS_SLOW (0 << 0)
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#define AT91_PMC_CSS_MAIN (1 << 0)
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@ -111,27 +123,27 @@
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#define AT91_PMC_PLLADIV2_OFF (0 << 12)
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#define AT91_PMC_PLLADIV2_ON (1 << 12)
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#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
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#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
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#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
|
||||
#define AT91_PMC_USBS_PLLA (0 << 0)
|
||||
#define AT91_PMC_USBS_UPLL (1 << 0)
|
||||
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
||||
|
||||
#define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */
|
||||
#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
|
||||
#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
|
||||
#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
|
||||
#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
|
||||
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
||||
#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
||||
#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
|
||||
#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
|
||||
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
||||
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
||||
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
||||
|
||||
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
|
||||
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
|
||||
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
|
||||
#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
|
||||
#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
|
||||
#define AT91_PMC_SR 0x68 /* Status Register */
|
||||
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
|
||||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||
|
|
@ -144,18 +156,18 @@
|
|||
#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
|
||||
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
|
||||
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
|
||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */
|
||||
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
|
||||
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
|
||||
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
|
||||
#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
|
||||
|
||||
#define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */
|
||||
#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
|
||||
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
|
||||
|
||||
#define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */
|
||||
#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */
|
||||
#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
|
||||
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
|
||||
#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */
|
||||
|
|
|
|||
|
|
@ -77,10 +77,8 @@
|
|||
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
|
||||
|
||||
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
|
||||
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
|
||||
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
|
||||
|
|
|
|||
|
|
@ -80,7 +80,6 @@
|
|||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9260_BASE_ECC 0xffffe800
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@
|
|||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9261_BASE_SMC 0xffffec00
|
||||
|
|
|
|||
|
|
@ -74,7 +74,6 @@
|
|||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9263_BASE_ECC0 0xffffe000
|
||||
|
|
|
|||
|
|
@ -86,7 +86,6 @@
|
|||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9G45_BASE_ECC 0xffffe200
|
||||
|
|
|
|||
|
|
@ -69,7 +69,6 @@
|
|||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
|
|
|
|||
|
|
@ -55,10 +55,9 @@
|
|||
#define AT91SAM9X5_BASE_USART2 0xf8024000
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
|
||||
/*
|
||||
* Base addresses for early serial code (uncompress.h)
|
||||
|
|
|
|||
|
|
@ -59,9 +59,10 @@
|
|||
|
||||
/*
|
||||
* On all at91 have the Advanced Interrupt Controller starts at address
|
||||
* 0xfffff000
|
||||
* 0xfffff000 and the Power Management Controller starts at 0xfffffc00
|
||||
*/
|
||||
#define AT91_AIC 0xfffff000
|
||||
#define AT91_PMC 0xfffffc00
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ static int at91_pm_verify_clocks(void)
|
|||
unsigned long scsr;
|
||||
int i;
|
||||
|
||||
scsr = at91_sys_read(AT91_PMC_SCSR);
|
||||
scsr = at91_pmc_read(AT91_PMC_SCSR);
|
||||
|
||||
/* USB must not be using PLLB */
|
||||
if (cpu_is_at91rm9200()) {
|
||||
|
|
@ -160,7 +160,7 @@ static int at91_pm_verify_clocks(void)
|
|||
if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
|
||||
continue;
|
||||
|
||||
css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
|
||||
css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
|
||||
if (css != AT91_PMC_CSS_SLOW) {
|
||||
pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
|
||||
return 0;
|
||||
|
|
@ -197,7 +197,6 @@ extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
|
|||
extern u32 at91_slow_clock_sz;
|
||||
#endif
|
||||
|
||||
static void __iomem *at91_pmc_base = (void __iomem*)(AT91_VA_BASE_SYS + AT91_PMC);
|
||||
void __iomem *at91_ramc_base[2];
|
||||
|
||||
void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
|
||||
|
|
@ -218,7 +217,7 @@ static int at91_pm_enter(suspend_state_t state)
|
|||
|
||||
pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
|
||||
/* remember all the always-wake irqs */
|
||||
(at91_sys_read(AT91_PMC_PCSR)
|
||||
(at91_pmc_read(AT91_PMC_PCSR)
|
||||
| (1 << AT91_ID_FIQ)
|
||||
| (1 << AT91_ID_SYS)
|
||||
| (at91_extern_irq))
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ tmp2 .req r5
|
|||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MCKRDY
|
||||
beq 1b
|
||||
2:
|
||||
|
|
@ -68,7 +68,7 @@ tmp2 .req r5
|
|||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MOSCS
|
||||
beq 1b
|
||||
2:
|
||||
|
|
@ -82,7 +82,7 @@ tmp2 .req r5
|
|||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKA
|
||||
beq 1b
|
||||
2:
|
||||
|
|
@ -96,7 +96,7 @@ tmp2 .req r5
|
|||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #(AT91_PMC_SR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKB
|
||||
beq 1b
|
||||
2:
|
||||
|
|
@ -176,14 +176,14 @@ sdr_sr_enable:
|
|||
|
||||
sdr_sr_done:
|
||||
/* Save Master clock setting */
|
||||
ldr tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
str tmp1, .saved_mckr
|
||||
|
||||
/*
|
||||
* Set the Master clock source to slow clock
|
||||
*/
|
||||
bic tmp1, tmp1, #AT91_PMC_CSS
|
||||
str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
|
|
@ -194,44 +194,44 @@ sdr_sr_done:
|
|||
* See AT91RM9200 errata #27 and #28 for details.
|
||||
*/
|
||||
mov tmp1, #0
|
||||
str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
#endif
|
||||
|
||||
/* Save PLLA setting and disable it */
|
||||
ldr tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
str tmp1, .saved_pllar
|
||||
|
||||
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
|
||||
str tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
/* Save PLLB setting and disable it */
|
||||
ldr tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
str tmp1, .saved_pllbr
|
||||
|
||||
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||
str tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
|
||||
/* Turn off the main oscillator */
|
||||
ldr tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
bic tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
str tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
/* Wait for interrupt */
|
||||
mcr p15, 0, tmp1, c7, c0, 4
|
||||
|
||||
/* Turn on the main oscillator */
|
||||
ldr tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)]
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
orr tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
str tmp1, [pmc, #(AT91_CKGR_MOR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
wait_moscrdy
|
||||
|
||||
/* Restore PLLB setting */
|
||||
ldr tmp1, .saved_pllbr
|
||||
str tmp1, [pmc, #(AT91_CKGR_PLLBR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
|
||||
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||
bne 1f
|
||||
|
|
@ -243,7 +243,7 @@ sdr_sr_done:
|
|||
|
||||
/* Restore PLLA setting */
|
||||
ldr tmp1, .saved_pllar
|
||||
str tmp1, [pmc, #(AT91_CKGR_PLLAR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||
bne 3f
|
||||
|
|
@ -264,7 +264,7 @@ sdr_sr_done:
|
|||
tst tmp1, #AT91_PMC_PRES
|
||||
beq 2f
|
||||
and tmp1, tmp1, #AT91_PMC_PRES
|
||||
str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
#endif
|
||||
|
|
@ -273,7 +273,7 @@ sdr_sr_done:
|
|||
* Restore master clock setting
|
||||
*/
|
||||
2: ldr tmp1, .saved_mckr
|
||||
str tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
|
|
|
|||
|
|
@ -332,12 +332,12 @@ static int vbus_is_present(struct usba_udc *udc)
|
|||
|
||||
static void toggle_bias(int is_on)
|
||||
{
|
||||
unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
|
||||
unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
|
||||
|
||||
if (is_on)
|
||||
at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
|
||||
at91_pmc_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
|
||||
else
|
||||
at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
|
||||
at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
|
||||
}
|
||||
|
||||
#else
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue