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MIPS: mm: Add MIPS R6 instruction encodings

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MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Leonid Yegoshin 2014-11-19 09:29:42 +00:00 • committed by Markos Chandras
commit a168b8f1cd
2 changed files with 38 additions and 3 deletions
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9
arch/mips/include/uapi/asm/inst.h
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@ -83,9 +83,12 @@ enum spec3_op {
swe_op = 0x1f, bshfl_op = 0x20,
swle_op = 0x21, swre_op = 0x22,
prefe_op = 0x23, dbshfl_op = 0x24,
lbue_op = 0x28, lhue_op = 0x29,
lbe_op = 0x2c, lhe_op = 0x2d,
lle_op = 0x2e, lwe_op = 0x2f,
cache6_op = 0x25, sc6_op = 0x26,
scd6_op = 0x27, lbue_op = 0x28,
lhue_op = 0x29, lbe_op = 0x2c,
lhe_op = 0x2d, lle_op = 0x2e,
lwe_op = 0x2f, pref6_op = 0x35,
ll6_op = 0x36, lld6_op = 0x37,
rdhwr_op = 0x3b
};