clk: zynq: Remove deprecated clock code
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-doc@vger.kernel.org Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Soren Brinkmann
Michal Simek
parent
30e1e28598
commit
97c4e87d45
2 changed files with 0 additions and 426 deletions
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@ -102,51 +102,3 @@ Example:
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clocks = <&clkc 16>, <&clk_foo>;
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clocks = <&clkc 16>, <&clk_foo>;
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clock-names = "gem1_emio_clk", "can_mio_clk_23";
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clock-names = "gem1_emio_clk", "can_mio_clk_23";
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};
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};
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== PLLs ==
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Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
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Required properties:
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- #clock-cells : shall be 0 (only one clock is output from this node)
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- compatible : "xlnx,zynq-pll"
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- reg : pair of u32 values, which are the address offsets within the SLCR
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of the relevant PLL_CTRL register and PLL_CFG register respectively
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- clocks : phandle for parent clock. should be the phandle for ps_clk
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Optional properties:
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- clock-output-names : name of the output clock
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Example:
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armpll: armpll {
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#clock-cells = <0>;
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compatible = "xlnx,zynq-pll";
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clocks = <&ps_clk>;
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reg = <0x100 0x110>;
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clock-output-names = "armpll";
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};
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== Peripheral clocks ==
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Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
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Required properties:
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- #clock-cells : shall be 1
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- compatible : "xlnx,zynq-periph-clock"
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- reg : a single u32 value, describing the offset within the SLCR where
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the CLK_CTRL register is found for this peripheral
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- clocks : phandle for parent clocks. should hold phandles for
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the IO_PLL, ARM_PLL, and DDR_PLL in order
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- clock-output-names : names of the output clock(s). For peripherals that have
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two output clocks (for example, the UART), two clocks
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should be listed.
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Example:
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uart_clk: uart_clk {
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#clock-cells = <1>;
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compatible = "xlnx,zynq-periph-clock";
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clocks = <&iopll &armpll &ddrpll>;
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reg = <0x154>;
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clock-output-names = "uart0_ref_clk",
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"uart1_ref_clk";
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};
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@ -1,378 +0,0 @@
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/*
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* Copyright (c) 2012 National Instruments
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*
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* Josh Cartwright <josh.cartwright@ni.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/zynq.h>
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static void __iomem *slcr_base;
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struct zynq_pll_clk {
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struct clk_hw hw;
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void __iomem *pll_ctrl;
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void __iomem *pll_cfg;
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};
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#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw)
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#define CTRL_PLL_FDIV(x) ((x) >> 12)
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static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct zynq_pll_clk *pll = to_zynq_pll_clk(hw);
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return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl));
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}
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static const struct clk_ops zynq_pll_clk_ops = {
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.recalc_rate = zynq_pll_recalc_rate,
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};
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static void __init zynq_pll_clk_setup(struct device_node *np)
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{
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struct clk_init_data init;
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struct zynq_pll_clk *pll;
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const char *parent_name;
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struct clk *clk;
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u32 regs[2];
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int ret;
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ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs));
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if (WARN_ON(ret))
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return;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (WARN_ON(!pll))
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return;
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pll->pll_ctrl = slcr_base + regs[0];
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pll->pll_cfg = slcr_base + regs[1];
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of_property_read_string(np, "clock-output-names", &init.name);
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init.ops = &zynq_pll_clk_ops;
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parent_name = of_clk_get_parent_name(np, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll->hw.init = &init;
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clk = clk_register(NULL, &pll->hw);
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if (WARN_ON(IS_ERR(clk)))
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return;
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ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
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if (WARN_ON(ret))
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return;
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}
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CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup);
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struct zynq_periph_clk {
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struct clk_hw hw;
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struct clk_onecell_data onecell_data;
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struct clk *gates[2];
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void __iomem *clk_ctrl;
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spinlock_t clkact_lock;
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};
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#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw)
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static const u8 periph_clk_parent_map[] = {
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0, 0, 1, 2
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};
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#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4])
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#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
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static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
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return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl));
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}
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static u8 zynq_periph_get_parent(struct clk_hw *hw)
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{
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struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
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return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl));
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}
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static const struct clk_ops zynq_periph_clk_ops = {
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.recalc_rate = zynq_periph_recalc_rate,
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.get_parent = zynq_periph_get_parent,
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};
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static void __init zynq_periph_clk_setup(struct device_node *np)
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{
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struct zynq_periph_clk *periph;
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const char *parent_names[3];
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struct clk_init_data init;
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int clk_num = 0, err;
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const char *name;
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struct clk *clk;
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u32 reg;
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int i;
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err = of_property_read_u32(np, "reg", ®);
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if (WARN_ON(err))
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return;
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periph = kzalloc(sizeof(*periph), GFP_KERNEL);
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if (WARN_ON(!periph))
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return;
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periph->clk_ctrl = slcr_base + reg;
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spin_lock_init(&periph->clkact_lock);
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init.name = np->name;
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init.ops = &zynq_periph_clk_ops;
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for (i = 0; i < ARRAY_SIZE(parent_names); i++)
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parent_names[i] = of_clk_get_parent_name(np, i);
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init.parent_names = parent_names;
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init.num_parents = ARRAY_SIZE(parent_names);
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periph->hw.init = &init;
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clk = clk_register(NULL, &periph->hw);
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if (WARN_ON(IS_ERR(clk)))
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return;
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err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
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if (WARN_ON(err))
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return;
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err = of_property_read_string_index(np, "clock-output-names", 0,
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&name);
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if (WARN_ON(err))
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return;
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periph->gates[0] = clk_register_gate(NULL, name, np->name, 0,
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periph->clk_ctrl, 0, 0,
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&periph->clkact_lock);
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if (WARN_ON(IS_ERR(periph->gates[0])))
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return;
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clk_num++;
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/* some periph clks have 2 downstream gates */
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err = of_property_read_string_index(np, "clock-output-names", 1,
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&name);
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if (err != -ENODATA) {
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periph->gates[1] = clk_register_gate(NULL, name, np->name, 0,
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periph->clk_ctrl, 1, 0,
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&periph->clkact_lock);
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if (WARN_ON(IS_ERR(periph->gates[1])))
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return;
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clk_num++;
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}
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periph->onecell_data.clks = periph->gates;
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periph->onecell_data.clk_num = clk_num;
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err = of_clk_add_provider(np, of_clk_src_onecell_get,
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&periph->onecell_data);
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if (WARN_ON(err))
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return;
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}
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CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup);
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/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
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* derivative rates depend on CLK_621_TRUE
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*/
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struct zynq_cpu_clk {
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struct clk_hw hw;
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struct clk_onecell_data onecell_data;
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struct clk *subclks[4];
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void __iomem *clk_ctrl;
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spinlock_t clkact_lock;
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};
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#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw)
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static const u8 zynq_cpu_clk_parent_map[] = {
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1, 1, 2, 0
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};
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#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
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#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
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static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw)
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{
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struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
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return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl));
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}
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static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
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return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl));
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}
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static const struct clk_ops zynq_cpu_clk_ops = {
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.get_parent = zynq_cpu_clk_get_parent,
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.recalc_rate = zynq_cpu_clk_recalc_rate,
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};
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struct zynq_cpu_subclk {
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struct clk_hw hw;
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void __iomem *clk_621;
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enum {
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CPU_SUBCLK_6X4X,
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CPU_SUBCLK_3X2X,
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CPU_SUBCLK_2X,
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CPU_SUBCLK_1X,
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} which;
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};
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#define CLK_621_TRUE(x) ((x) & 1)
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#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw);
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static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long uninitialized_var(rate);
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struct zynq_cpu_subclk *subclk;
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bool is_621;
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subclk = to_zynq_cpu_subclk(hw)
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is_621 = CLK_621_TRUE(ioread32(subclk->clk_621));
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switch (subclk->which) {
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case CPU_SUBCLK_6X4X:
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rate = parent_rate;
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break;
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case CPU_SUBCLK_3X2X:
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rate = parent_rate / 2;
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break;
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case CPU_SUBCLK_2X:
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rate = parent_rate / (is_621 ? 3 : 2);
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break;
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case CPU_SUBCLK_1X:
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rate = parent_rate / (is_621 ? 6 : 4);
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break;
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};
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return rate;
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}
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static const struct clk_ops zynq_cpu_subclk_ops = {
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.recalc_rate = zynq_cpu_subclk_recalc_rate,
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};
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static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which,
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void __iomem *clk_621)
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{
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struct zynq_cpu_subclk *subclk;
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struct clk_init_data init;
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struct clk *clk;
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int err;
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err = of_property_read_string_index(np, "clock-output-names",
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which, &init.name);
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if (WARN_ON(err))
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goto err_read_output_name;
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subclk = kzalloc(sizeof(*subclk), GFP_KERNEL);
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if (!subclk)
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goto err_subclk_alloc;
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subclk->clk_621 = clk_621;
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subclk->which = which;
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init.ops = &zynq_cpu_subclk_ops;
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init.parent_names = &np->name;
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init.num_parents = 1;
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subclk->hw.init = &init;
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clk = clk_register(NULL, &subclk->hw);
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if (WARN_ON(IS_ERR(clk)))
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goto err_clk_register;
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return clk;
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err_clk_register:
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kfree(subclk);
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||||||
err_subclk_alloc:
|
|
||||||
err_read_output_name:
|
|
||||||
return ERR_PTR(-EINVAL);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void __init zynq_cpu_clk_setup(struct device_node *np)
|
|
||||||
{
|
|
||||||
struct zynq_cpu_clk *cpuclk;
|
|
||||||
const char *parent_names[3];
|
|
||||||
struct clk_init_data init;
|
|
||||||
void __iomem *clk_621;
|
|
||||||
struct clk *clk;
|
|
||||||
u32 reg[2];
|
|
||||||
int err;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
|
|
||||||
if (WARN_ON(err))
|
|
||||||
return;
|
|
||||||
|
|
||||||
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
|
|
||||||
if (WARN_ON(!cpuclk))
|
|
||||||
return;
|
|
||||||
|
|
||||||
cpuclk->clk_ctrl = slcr_base + reg[0];
|
|
||||||
clk_621 = slcr_base + reg[1];
|
|
||||||
spin_lock_init(&cpuclk->clkact_lock);
|
|
||||||
|
|
||||||
init.name = np->name;
|
|
||||||
init.ops = &zynq_cpu_clk_ops;
|
|
||||||
for (i = 0; i < ARRAY_SIZE(parent_names); i++)
|
|
||||||
parent_names[i] = of_clk_get_parent_name(np, i);
|
|
||||||
init.parent_names = parent_names;
|
|
||||||
init.num_parents = ARRAY_SIZE(parent_names);
|
|
||||||
|
|
||||||
cpuclk->hw.init = &init;
|
|
||||||
|
|
||||||
clk = clk_register(NULL, &cpuclk->hw);
|
|
||||||
if (WARN_ON(IS_ERR(clk)))
|
|
||||||
return;
|
|
||||||
|
|
||||||
err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
||||||
if (WARN_ON(err))
|
|
||||||
return;
|
|
||||||
|
|
||||||
for (i = 0; i < 4; i++) {
|
|
||||||
cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621);
|
|
||||||
if (WARN_ON(IS_ERR(cpuclk->subclks[i])))
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
cpuclk->onecell_data.clks = cpuclk->subclks;
|
|
||||||
cpuclk->onecell_data.clk_num = i;
|
|
||||||
|
|
||||||
err = of_clk_add_provider(np, of_clk_src_onecell_get,
|
|
||||||
&cpuclk->onecell_data);
|
|
||||||
if (WARN_ON(err))
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup);
|
|
||||||
|
|
||||||
void __init xilinx_zynq_clocks_init(void __iomem *slcr)
|
|
||||||
{
|
|
||||||
slcr_base = slcr;
|
|
||||||
of_clk_init(NULL);
|
|
||||||
}
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue