[PATCH] x86_64: mce_amd support for family 0x10 processors
Add support for mce threshold registers found in future AMD family 0x10 processors. Backwards compatible with family 0xF hardware. AK: fixed build on !SMP Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Jacob Shin
Linus Torvalds
parent
fff2e89f11
commit
9526866439
2 changed files with 298 additions and 77 deletions
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@ -1,5 +1,5 @@
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/*
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* (c) 2005 Advanced Micro Devices, Inc.
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* (c) 2005, 2006 Advanced Micro Devices, Inc.
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* Your use of this code is subject to the terms and conditions of the
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* GNU general public license version 2. See "COPYING" or
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* http://www.gnu.org/licenses/gpl.html
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@ -8,9 +8,10 @@
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*
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* Support : jacob.shin@amd.com
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*
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* MC4_MISC0 DRAM ECC Error Threshold available under AMD K8 Rev F.
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* MC4_MISC0 exists per physical processor.
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* April 2006
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* - added support for AMD Family 0x10 processors
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*
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* All MC4_MISCi registers are shared between multi-cores
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*/
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#include <linux/cpu.h>
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@ -30,8 +31,9 @@
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#include <asm/idle.h>
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#define PFX "mce_threshold: "
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#define VERSION "version 1.0.10"
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#define NR_BANKS 5
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#define VERSION "version 1.1.0"
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#define NR_BANKS 6
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#define NR_BLOCKS 9
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#define THRESHOLD_MAX 0xFFF
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#define INT_TYPE_APIC 0x00020000
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#define MASK_VALID_HI 0x80000000
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@ -40,21 +42,33 @@
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#define MASK_INT_TYPE_HI 0x00060000
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#define MASK_OVERFLOW_HI 0x00010000
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#define MASK_ERR_COUNT_HI 0x00000FFF
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#define MASK_OVERFLOW 0x0001000000000000L
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#define MASK_BLKPTR_LO 0xFF000000
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#define MCG_XBLK_ADDR 0xC0000400
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struct threshold_bank {
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struct threshold_block {
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unsigned int block;
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unsigned int bank;
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unsigned int cpu;
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u8 bank;
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u8 interrupt_enable;
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u32 address;
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u16 interrupt_enable;
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u16 threshold_limit;
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struct kobject kobj;
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struct list_head miscj;
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};
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static struct threshold_bank threshold_defaults = {
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/* defaults used early on boot */
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static struct threshold_block threshold_defaults = {
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.interrupt_enable = 0,
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.threshold_limit = THRESHOLD_MAX,
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};
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struct threshold_bank {
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struct kobject kobj;
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struct threshold_block *blocks;
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cpumask_t cpus;
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};
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static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
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#ifdef CONFIG_SMP
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static unsigned char shared_bank[NR_BANKS] = {
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0, 0, 0, 0, 1
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@ -68,12 +82,12 @@ static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
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*/
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/* must be called with correct cpu affinity */
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static void threshold_restart_bank(struct threshold_bank *b,
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static void threshold_restart_bank(struct threshold_block *b,
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int reset, u16 old_limit)
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{
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u32 mci_misc_hi, mci_misc_lo;
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rdmsr(MSR_IA32_MC0_MISC + b->bank * 4, mci_misc_lo, mci_misc_hi);
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rdmsr(b->address, mci_misc_lo, mci_misc_hi);
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if (b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
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reset = 1; /* limit cannot be lower than err count */
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@ -94,37 +108,59 @@ static void threshold_restart_bank(struct threshold_bank *b,
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(mci_misc_hi &= ~MASK_INT_TYPE_HI);
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mci_misc_hi |= MASK_COUNT_EN_HI;
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wrmsr(MSR_IA32_MC0_MISC + b->bank * 4, mci_misc_lo, mci_misc_hi);
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wrmsr(b->address, mci_misc_lo, mci_misc_hi);
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}
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/* cpu init entry point, called from mce.c with preempt off */
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void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
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{
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int bank;
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u32 mci_misc_lo, mci_misc_hi;
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unsigned int bank, block;
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unsigned int cpu = smp_processor_id();
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u32 low = 0, high = 0, address = 0;
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for (bank = 0; bank < NR_BANKS; ++bank) {
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rdmsr(MSR_IA32_MC0_MISC + bank * 4, mci_misc_lo, mci_misc_hi);
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for (block = 0; block < NR_BLOCKS; ++block) {
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if (block == 0)
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address = MSR_IA32_MC0_MISC + bank * 4;
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else if (block == 1)
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address = MCG_XBLK_ADDR
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+ ((low & MASK_BLKPTR_LO) >> 21);
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else
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++address;
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/* !valid, !counter present, bios locked */
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if (!(mci_misc_hi & MASK_VALID_HI) ||
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!(mci_misc_hi & MASK_VALID_HI >> 1) ||
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(mci_misc_hi & MASK_VALID_HI >> 2))
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if (rdmsr_safe(address, &low, &high))
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continue;
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per_cpu(bank_map, cpu) |= (1 << bank);
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if (!(high & MASK_VALID_HI)) {
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if (block)
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continue;
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else
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break;
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}
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if (!(high & MASK_VALID_HI >> 1) ||
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(high & MASK_VALID_HI >> 2))
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continue;
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if (!block)
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per_cpu(bank_map, cpu) |= (1 << bank);
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#ifdef CONFIG_SMP
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if (shared_bank[bank] && c->cpu_core_id)
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continue;
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break;
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#endif
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high &= ~MASK_LVTOFF_HI;
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high |= K8_APIC_EXT_LVT_ENTRY_THRESHOLD << 20;
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wrmsr(address, low, high);
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setup_threshold_lvt((mci_misc_hi & MASK_LVTOFF_HI) >> 20);
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threshold_defaults.cpu = cpu;
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threshold_defaults.bank = bank;
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setup_APIC_extened_lvt(K8_APIC_EXT_LVT_ENTRY_THRESHOLD,
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THRESHOLD_APIC_VECTOR,
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K8_APIC_EXT_INT_MSG_FIX, 0);
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threshold_defaults.address = address;
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threshold_restart_bank(&threshold_defaults, 0, 0);
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}
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}
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}
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/*
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* APIC Interrupt Handler
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@ -137,8 +173,9 @@ void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
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*/
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asmlinkage void mce_threshold_interrupt(void)
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{
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int bank;
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unsigned int bank, block;
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struct mce m;
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u32 low = 0, high = 0, address = 0;
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ack_APIC_irq();
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exit_idle();
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@ -150,14 +187,41 @@ asmlinkage void mce_threshold_interrupt(void)
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/* assume first bank caused it */
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for (bank = 0; bank < NR_BANKS; ++bank) {
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m.bank = MCE_THRESHOLD_BASE + bank;
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rdmsrl(MSR_IA32_MC0_MISC + bank * 4, m.misc);
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for (block = 0; block < NR_BLOCKS; ++block) {
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if (block == 0)
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address = MSR_IA32_MC0_MISC + bank * 4;
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else if (block == 1)
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address = MCG_XBLK_ADDR
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+ ((low & MASK_BLKPTR_LO) >> 21);
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else
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++address;
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if (m.misc & MASK_OVERFLOW) {
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if (rdmsr_safe(address, &low, &high))
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continue;
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if (!(high & MASK_VALID_HI)) {
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if (block)
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continue;
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else
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break;
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}
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if (!(high & MASK_VALID_HI >> 1) ||
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(high & MASK_VALID_HI >> 2))
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continue;
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if (high & MASK_OVERFLOW_HI) {
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rdmsrl(address, m.misc);
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rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
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m.status);
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m.bank = K8_MCE_THRESHOLD_BASE
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+ bank * NR_BLOCKS
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+ block;
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mce_log(&m);
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goto out;
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}
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}
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}
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out:
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irq_exit();
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}
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@ -168,12 +232,10 @@ asmlinkage void mce_threshold_interrupt(void)
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struct threshold_attr {
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struct attribute attr;
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ssize_t(*show) (struct threshold_bank *, char *);
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ssize_t(*store) (struct threshold_bank *, const char *, size_t count);
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ssize_t(*show) (struct threshold_block *, char *);
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ssize_t(*store) (struct threshold_block *, const char *, size_t count);
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};
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static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
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static cpumask_t affinity_set(unsigned int cpu)
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{
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cpumask_t oldmask = current->cpus_allowed;
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@ -189,14 +251,14 @@ static void affinity_restore(cpumask_t oldmask)
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}
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#define SHOW_FIELDS(name) \
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static ssize_t show_ ## name(struct threshold_bank * b, char *buf) \
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static ssize_t show_ ## name(struct threshold_block * b, char *buf) \
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{ \
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return sprintf(buf, "%lx\n", (unsigned long) b->name); \
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}
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SHOW_FIELDS(interrupt_enable)
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SHOW_FIELDS(threshold_limit)
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static ssize_t store_interrupt_enable(struct threshold_bank *b,
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static ssize_t store_interrupt_enable(struct threshold_block *b,
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const char *buf, size_t count)
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{
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char *end;
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@ -213,7 +275,7 @@ static ssize_t store_interrupt_enable(struct threshold_bank *b,
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return end - buf;
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}
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static ssize_t store_threshold_limit(struct threshold_bank *b,
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static ssize_t store_threshold_limit(struct threshold_block *b,
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const char *buf, size_t count)
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{
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char *end;
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@ -236,18 +298,18 @@ static ssize_t store_threshold_limit(struct threshold_bank *b,
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return end - buf;
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}
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static ssize_t show_error_count(struct threshold_bank *b, char *buf)
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static ssize_t show_error_count(struct threshold_block *b, char *buf)
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{
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u32 high, low;
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cpumask_t oldmask;
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oldmask = affinity_set(b->cpu);
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rdmsr(MSR_IA32_MC0_MISC + b->bank * 4, low, high); /* ignore low 32 */
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rdmsr(b->address, low, high);
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affinity_restore(oldmask);
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return sprintf(buf, "%x\n",
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(high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
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}
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static ssize_t store_error_count(struct threshold_bank *b,
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static ssize_t store_error_count(struct threshold_block *b,
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const char *buf, size_t count)
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{
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cpumask_t oldmask;
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@ -278,12 +340,12 @@ static struct attribute *default_attrs[] = {
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NULL
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};
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#define to_bank(k) container_of(k,struct threshold_bank,kobj)
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#define to_block(k) container_of(k, struct threshold_block, kobj)
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#define to_attr(a) container_of(a,struct threshold_attr,attr)
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static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
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{
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struct threshold_bank *b = to_bank(kobj);
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struct threshold_block *b = to_block(kobj);
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struct threshold_attr *a = to_attr(attr);
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ssize_t ret;
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ret = a->show ? a->show(b, buf) : -EIO;
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@ -293,7 +355,7 @@ static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
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static ssize_t store(struct kobject *kobj, struct attribute *attr,
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const char *buf, size_t count)
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{
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struct threshold_bank *b = to_bank(kobj);
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struct threshold_block *b = to_block(kobj);
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struct threshold_attr *a = to_attr(attr);
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ssize_t ret;
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ret = a->store ? a->store(b, buf, count) : -EIO;
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@ -310,53 +372,164 @@ static struct kobj_type threshold_ktype = {
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.default_attrs = default_attrs,
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};
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/* symlinks sibling shared banks to first core. first core owns dir/files. */
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static __cpuinit int threshold_create_bank(unsigned int cpu, int bank)
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static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
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unsigned int bank,
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unsigned int block,
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u32 address)
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{
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int err = 0;
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int err;
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u32 low, high;
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struct threshold_block *b = NULL;
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if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
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return 0;
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if (rdmsr_safe(address, &low, &high))
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goto recurse;
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if (!(high & MASK_VALID_HI)) {
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if (block)
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goto recurse;
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else
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return 0;
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}
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if (!(high & MASK_VALID_HI >> 1) ||
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(high & MASK_VALID_HI >> 2))
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goto recurse;
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b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
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if (!b)
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return -ENOMEM;
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memset(b, 0, sizeof(struct threshold_block));
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b->block = block;
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b->bank = bank;
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b->cpu = cpu;
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b->address = address;
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b->interrupt_enable = 0;
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b->threshold_limit = THRESHOLD_MAX;
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INIT_LIST_HEAD(&b->miscj);
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if (per_cpu(threshold_banks, cpu)[bank]->blocks)
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list_add(&b->miscj,
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&per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
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else
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per_cpu(threshold_banks, cpu)[bank]->blocks = b;
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kobject_set_name(&b->kobj, "misc%i", block);
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b->kobj.parent = &per_cpu(threshold_banks, cpu)[bank]->kobj;
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b->kobj.ktype = &threshold_ktype;
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err = kobject_register(&b->kobj);
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if (err)
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goto out_free;
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recurse:
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if (!block) {
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address = (low & MASK_BLKPTR_LO) >> 21;
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if (!address)
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return 0;
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address += MCG_XBLK_ADDR;
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} else
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++address;
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err = allocate_threshold_blocks(cpu, bank, ++block, address);
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if (err)
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goto out_free;
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return err;
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out_free:
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if (b) {
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kobject_unregister(&b->kobj);
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kfree(b);
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}
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return err;
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}
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/* symlinks sibling shared banks to first core. first core owns dir/files. */
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static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
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{
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int i, err = 0;
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struct threshold_bank *b = NULL;
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cpumask_t oldmask = CPU_MASK_NONE;
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char name[32];
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sprintf(name, "threshold_bank%i", bank);
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#ifdef CONFIG_SMP
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if (cpu_data[cpu].cpu_core_id && shared_bank[bank]) { /* symlink */
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char name[16];
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unsigned lcpu = first_cpu(cpu_core_map[cpu]);
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if (cpu_data[lcpu].cpu_core_id)
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goto out; /* first core not up yet */
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i = first_cpu(cpu_core_map[cpu]);
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/* first core not up yet */
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if (cpu_data[i].cpu_core_id)
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goto out;
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/* already linked */
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if (per_cpu(threshold_banks, cpu)[bank])
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goto out;
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b = per_cpu(threshold_banks, i)[bank];
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b = per_cpu(threshold_banks, lcpu)[bank];
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if (!b)
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goto out;
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sprintf(name, "threshold_bank%i", bank);
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err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
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&b->kobj, name);
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if (err)
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goto out;
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b->cpus = cpu_core_map[cpu];
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per_cpu(threshold_banks, cpu)[bank] = b;
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goto out;
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}
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#endif
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b = kmalloc(sizeof(struct threshold_bank), GFP_KERNEL);
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b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
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if (!b) {
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err = -ENOMEM;
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goto out;
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}
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memset(b, 0, sizeof(struct threshold_bank));
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b->cpu = cpu;
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b->bank = bank;
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b->interrupt_enable = 0;
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b->threshold_limit = THRESHOLD_MAX;
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kobject_set_name(&b->kobj, "threshold_bank%i", bank);
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b->kobj.parent = &per_cpu(device_mce, cpu).kobj;
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b->kobj.ktype = &threshold_ktype;
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#ifndef CONFIG_SMP
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b->cpus = CPU_MASK_ALL;
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#else
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b->cpus = cpu_core_map[cpu];
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#endif
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err = kobject_register(&b->kobj);
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if (err) {
|
||||
kfree(b);
|
||||
goto out;
|
||||
}
|
||||
if (err)
|
||||
goto out_free;
|
||||
|
||||
per_cpu(threshold_banks, cpu)[bank] = b;
|
||||
|
||||
oldmask = affinity_set(cpu);
|
||||
err = allocate_threshold_blocks(cpu, bank, 0,
|
||||
MSR_IA32_MC0_MISC + bank * 4);
|
||||
affinity_restore(oldmask);
|
||||
|
||||
if (err)
|
||||
goto out_free;
|
||||
|
||||
for_each_cpu_mask(i, b->cpus) {
|
||||
if (i == cpu)
|
||||
continue;
|
||||
|
||||
err = sysfs_create_link(&per_cpu(device_mce, i).kobj,
|
||||
&b->kobj, name);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
per_cpu(threshold_banks, i)[bank] = b;
|
||||
}
|
||||
|
||||
goto out;
|
||||
|
||||
out_free:
|
||||
per_cpu(threshold_banks, cpu)[bank] = NULL;
|
||||
kfree(b);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
|
@ -385,23 +558,64 @@ static __cpuinit int threshold_create_device(unsigned int cpu)
|
|||
* of shared sysfs dir/files, and rest of the cores will be symlinked to it.
|
||||
*/
|
||||
|
||||
/* cpu hotplug call removes all symlinks before first core dies */
|
||||
static __cpuinit void deallocate_threshold_block(unsigned int cpu,
|
||||
unsigned int bank)
|
||||
{
|
||||
struct threshold_block *pos = NULL;
|
||||
struct threshold_block *tmp = NULL;
|
||||
struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
|
||||
|
||||
if (!head)
|
||||
return;
|
||||
|
||||
list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
|
||||
kobject_unregister(&pos->kobj);
|
||||
list_del(&pos->miscj);
|
||||
kfree(pos);
|
||||
}
|
||||
|
||||
kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
|
||||
per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
|
||||
}
|
||||
|
||||
static __cpuinit void threshold_remove_bank(unsigned int cpu, int bank)
|
||||
{
|
||||
int i = 0;
|
||||
struct threshold_bank *b;
|
||||
char name[16];
|
||||
char name[32];
|
||||
|
||||
b = per_cpu(threshold_banks, cpu)[bank];
|
||||
|
||||
if (!b)
|
||||
return;
|
||||
if (shared_bank[bank] && atomic_read(&b->kobj.kref.refcount) > 2) {
|
||||
|
||||
if (!b->blocks)
|
||||
goto free_out;
|
||||
|
||||
sprintf(name, "threshold_bank%i", bank);
|
||||
|
||||
/* sibling symlink */
|
||||
if (shared_bank[bank] && b->blocks->cpu != cpu) {
|
||||
sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
|
||||
per_cpu(threshold_banks, cpu)[bank] = NULL;
|
||||
} else {
|
||||
kobject_unregister(&b->kobj);
|
||||
kfree(per_cpu(threshold_banks, cpu)[bank]);
|
||||
per_cpu(threshold_banks, i)[bank] = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
/* remove all sibling symlinks before unregistering */
|
||||
for_each_cpu_mask(i, b->cpus) {
|
||||
if (i == cpu)
|
||||
continue;
|
||||
|
||||
sysfs_remove_link(&per_cpu(device_mce, i).kobj, name);
|
||||
per_cpu(threshold_banks, i)[bank] = NULL;
|
||||
}
|
||||
|
||||
deallocate_threshold_block(cpu, bank);
|
||||
|
||||
free_out:
|
||||
kobject_unregister(&b->kobj);
|
||||
kfree(b);
|
||||
per_cpu(threshold_banks, cpu)[bank] = NULL;
|
||||
}
|
||||
|
||||
static __cpuinit void threshold_remove_device(unsigned int cpu)
|
||||
|
|
|
|||
|
|
@ -67,8 +67,15 @@ struct mce_log {
|
|||
/* Software defined banks */
|
||||
#define MCE_EXTENDED_BANK 128
|
||||
#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
|
||||
#define MCE_THRESHOLD_BASE MCE_EXTENDED_BANK + 1 /* MCE_AMD */
|
||||
#define MCE_THRESHOLD_DRAM_ECC MCE_THRESHOLD_BASE + 4
|
||||
|
||||
#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
|
||||
#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
|
||||
#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
|
||||
#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
|
||||
#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
|
||||
#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
|
||||
#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
|
||||
#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <asm/atomic.h>
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue