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PCI: tegra: Add Tegra 30 PCIe support

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Introduce a data structure to parameterize the driver according to SoC
generation, add Tegra30 specific code and update the device tree binding
document for Tegra30 support.

Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Jay Agarwal 2013-08-09 16:49:24 +02:00 • committed by Stephen Warren
parent d1523b52bf
commit 94716cddbe
2 changed files with 178 additions and 33 deletions
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4
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
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@ -1,7 +1,7 @@
NVIDIA Tegra PCIe controller
Required properties:
- compatible: "nvidia,tegra20-pcie"
- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
registers. Must contain an entry for each entry in the reg-names property.
@ -16,6 +16,7 @@ Required properties:
"msi": The Tegra interrupt that is asserted when an MSI is received
- pex-clk-supply: Supply voltage for internal reference clock
- vdd-supply: Power supply for controller (1.05V)
- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
- bus-range: Range of bus numbers associated with this controller
- #address-cells: Address representation for root ports (must be 3)
- cell 0 specifies the bus and device numbers of the root port:
@ -48,6 +49,7 @@ Required properties:
"afi": The Tegra clock of that name
"pcie_xclk": The Tegra clock of that name
"pll_e": The Tegra clock of that name
"cml": The Tegra clock of that name (not required for Tegra20)
Root ports are defined as subnodes of the PCIe controller node.