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irqchip: gic: use dmb ishst instead of dsb when raising a softirq

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When sending an SGI to another CPU, we require a barrier to ensure that
any pending stores to normal memory are made visible to the recipient
before the interrupt arrives.

Rather than use a vanilla dsb() (which will soon cause an assembly error
on arm64) before the writel_relaxed, we can instead use dsb(ishst),
since we just need to ensure that any pending normal writes are visible
within the inner-shareable domain before we poke the GIC.

With this observation, we can then further weaken the barrier to a
dmb(ishst), since other CPUs in the inner-shareable domain must observe
the write to the distributor before the SGI is generated.

Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Will Deacon 2014-02-20 17:42:07 +00:00 • committed by Arnd Bergmann
commit 8adbf57fc4
1 changed files with 2 additions and 2 deletions
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4
drivers/irqchip/irq-gic.c
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@ -661,9 +661,9 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
/* /*
* Ensure that stores to Normal memory are visible to the * Ensure that stores to Normal memory are visible to the
* other CPUs before issuing the IPI. * other CPUs before they observe us issuing the IPI.
*/ */
dsb(); dmb(ishst);
/* this always happens on GIC0 */ /* this always happens on GIC0 */
writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);