Merge branches 'regmap/irq' and 'regmap/cache' into regmap-next
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commit
81bf58eb3c
8 changed files with 361 additions and 3 deletions
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@ -25,7 +25,7 @@ enum regcache_type {
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REGCACHE_NONE,
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REGCACHE_INDEXED,
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REGCACHE_RBTREE,
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REGCACHE_LZO
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REGCACHE_COMPRESSED
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};
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/**
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@ -143,5 +143,53 @@ int regmap_update_bits(struct regmap *map, unsigned int reg,
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int regcache_sync(struct regmap *map);
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void regcache_cache_only(struct regmap *map, bool enable);
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void regcache_cache_bypass(struct regmap *map, bool enable);
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void regcache_mark_dirty(struct regmap *map);
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/**
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* Description of an IRQ for the generic regmap irq_chip.
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*
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* @reg_offset: Offset of the status/mask register within the bank
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* @mask: Mask used to flag/control the register.
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*/
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struct regmap_irq {
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unsigned int reg_offset;
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unsigned int mask;
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};
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/**
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* Description of a generic regmap irq_chip. This is not intended to
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* handle every possible interrupt controller, but it should handle a
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* substantial proportion of those that are found in the wild.
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*
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* @name: Descriptive name for IRQ controller.
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*
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* @status_base: Base status register address.
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* @mask_base: Base mask register address.
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* @ack_base: Base ack address. If zero then the chip is clear on read.
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*
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* @num_regs: Number of registers in each control bank.
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* @irqs: Descriptors for individual IRQs. Interrupt numbers are
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* assigned based on the index in the array of the interrupt.
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* @num_irqs: Number of descriptors.
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*/
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struct regmap_irq_chip {
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const char *name;
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unsigned int status_base;
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unsigned int mask_base;
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unsigned int ack_base;
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int num_regs;
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const struct regmap_irq *irqs;
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int num_irqs;
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};
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struct regmap_irq_chip_data;
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int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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int irq_base, struct regmap_irq_chip *chip,
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struct regmap_irq_chip_data **data);
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void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data);
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#endif
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