pch_can: Fix warnings
Currently, in case CONFIG_PM is disabled, compiler outputs warnings. Move six functions which are used only CONFIG_PM is enabled, into "#ifdef CONFIG_PM" area. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tomoya
David S. Miller
parent
1d5b4b2778
commit
7f2bc50efe
1 changed files with 73 additions and 73 deletions
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@ -245,23 +245,6 @@ static void pch_can_set_optmode(struct pch_can_priv *priv)
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iowrite32(reg_val, &priv->regs->opt);
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iowrite32(reg_val, &priv->regs->opt);
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}
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}
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static void pch_can_set_int_custom(struct pch_can_priv *priv)
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{
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/* Clearing the IE, SIE and EIE bits of Can control register. */
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pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
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/* Appropriately setting them. */
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pch_can_bit_set(&priv->regs->cont,
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((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
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}
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/* This function retrieves interrupt enabled for the CAN device. */
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static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
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{
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/* Obtaining the status of IE, SIE and EIE interrupt bits. */
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*enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
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}
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static void pch_can_set_int_enables(struct pch_can_priv *priv,
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static void pch_can_set_int_enables(struct pch_can_priv *priv,
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enum pch_can_mode interrupt_no)
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enum pch_can_mode interrupt_no)
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{
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{
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@ -355,61 +338,11 @@ static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
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pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
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pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
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}
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}
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static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
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enum pch_ifreg dir)
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{
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u32 ie, enable;
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if (dir)
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ie = PCH_IF_MCONT_RXIE;
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else
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ie = PCH_IF_MCONT_TXIE;
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
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if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
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((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
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enable = 1;
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} else {
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enable = 0;
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}
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return enable;
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}
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static int pch_can_int_pending(struct pch_can_priv *priv)
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static int pch_can_int_pending(struct pch_can_priv *priv)
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{
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{
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return ioread32(&priv->regs->intr) & 0xffff;
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return ioread32(&priv->regs->intr) & 0xffff;
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}
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}
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static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
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u32 buffer_num, u32 set)
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{
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
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&priv->regs->ifregs[0].cmask);
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if (set == PCH_ENABLE)
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_EOB);
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else
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pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
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}
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static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
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u32 buffer_num, u32 *link)
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{
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
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if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
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*link = PCH_DISABLE;
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else
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*link = PCH_ENABLE;
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}
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static void pch_can_clear_buffers(struct pch_can_priv *priv)
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static void pch_can_clear_buffers(struct pch_can_priv *priv)
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{
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{
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int i;
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int i;
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@ -583,12 +516,6 @@ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
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}
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}
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}
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}
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static int pch_can_get_buffer_status(struct pch_can_priv *priv)
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{
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return (ioread32(&priv->regs->treq1) & 0xffff) |
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((ioread32(&priv->regs->treq2) & 0xffff) << 16);
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}
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static void pch_can_reset(struct pch_can_priv *priv)
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static void pch_can_reset(struct pch_can_priv *priv)
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{
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{
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/* write to sw reset register */
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/* write to sw reset register */
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@ -1109,6 +1036,79 @@ static void __devexit pch_can_remove(struct pci_dev *pdev)
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}
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}
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#ifdef CONFIG_PM
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#ifdef CONFIG_PM
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static void pch_can_set_int_custom(struct pch_can_priv *priv)
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{
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/* Clearing the IE, SIE and EIE bits of Can control register. */
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pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
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/* Appropriately setting them. */
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pch_can_bit_set(&priv->regs->cont,
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((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
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}
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/* This function retrieves interrupt enabled for the CAN device. */
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static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
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{
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/* Obtaining the status of IE, SIE and EIE interrupt bits. */
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*enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
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}
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static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
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enum pch_ifreg dir)
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{
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u32 ie, enable;
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if (dir)
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ie = PCH_IF_MCONT_RXIE;
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else
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ie = PCH_IF_MCONT_TXIE;
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
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if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
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((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
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enable = 1;
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} else {
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enable = 0;
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}
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return enable;
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}
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static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
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u32 buffer_num, u32 set)
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{
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
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&priv->regs->ifregs[0].cmask);
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if (set == PCH_ENABLE)
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_EOB);
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else
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pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
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}
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static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
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u32 buffer_num, u32 *link)
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{
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
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if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
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*link = PCH_DISABLE;
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else
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*link = PCH_ENABLE;
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}
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static int pch_can_get_buffer_status(struct pch_can_priv *priv)
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{
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return (ioread32(&priv->regs->treq1) & 0xffff) |
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((ioread32(&priv->regs->treq2) & 0xffff) << 16);
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}
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static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
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static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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{
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int i; /* Counter variable. */
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int i; /* Counter variable. */
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