[SCSI] isci, firmware: Remove isci fallback parameter blob and generator
This parameter blob and generator program have been moved to the linux-firmware.git repository. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Ben Hutchings
James Bottomley
parent
798edaadba
commit
7d99b3abaf
6 changed files with 0 additions and 248 deletions
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@ -1,19 +0,0 @@
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# Makefile for create_fw
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#
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CC=gcc
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CFLAGS=-c -Wall -O2 -g
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LDFLAGS=
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SOURCES=create_fw.c
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OBJECTS=$(SOURCES:.cpp=.o)
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EXECUTABLE=create_fw
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all: $(SOURCES) $(EXECUTABLE)
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$(EXECUTABLE): $(OBJECTS)
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$(CC) $(LDFLAGS) $(OBJECTS) -o $@
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.c.o:
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$(CC) $(CFLAGS) $< -O $@
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clean:
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rm -f *.o $(EXECUTABLE)
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@ -1,36 +0,0 @@
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This defines the temporary binary blow we are to pass to the SCU
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driver to emulate the binary firmware that we will eventually be
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able to access via NVRAM on the SCU controller.
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The current size of the binary blob is expected to be 149 bytes or larger
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Header Types:
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0x1: Phy Masks
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0x2: Phy Gens
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0x3: SAS Addrs
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0xff: End of Data
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ID string - u8[12]: "#SCU MAGIC#\0"
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Version - u8: 1
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SubVersion - u8: 0
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Header Type - u8: 0x1
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Size - u8: 8
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Phy Mask - u32[8]
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Header Type - u8: 0x2
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Size - u8: 8
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Phy Gen - u32[8]
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Header Type - u8: 0x3
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Size - u8: 8
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Sas Addr - u64[8]
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Header Type - u8: 0xf
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==============================================================================
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Place isci_firmware.bin in /lib/firmware
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Be sure to recreate the initramfs image to include the firmware.
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@ -1,99 +0,0 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <string.h>
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#include <errno.h>
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#include <asm/types.h>
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#include <strings.h>
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#include <stdint.h>
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#include "create_fw.h"
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#include "../probe_roms.h"
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int write_blob(struct isci_orom *isci_orom)
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{
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FILE *fd;
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int err;
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size_t count;
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fd = fopen(blob_name, "w+");
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if (!fd) {
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perror("Open file for write failed");
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fclose(fd);
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return -EIO;
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}
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count = fwrite(isci_orom, sizeof(struct isci_orom), 1, fd);
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if (count != 1) {
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perror("Write data failed");
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fclose(fd);
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return -EIO;
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}
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fclose(fd);
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return 0;
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}
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void set_binary_values(struct isci_orom *isci_orom)
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{
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int ctrl_idx, phy_idx, port_idx;
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/* setting OROM signature */
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strncpy(isci_orom->hdr.signature, sig, strlen(sig));
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isci_orom->hdr.version = version;
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isci_orom->hdr.total_block_length = sizeof(struct isci_orom);
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isci_orom->hdr.hdr_length = sizeof(struct sci_bios_oem_param_block_hdr);
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isci_orom->hdr.num_elements = num_elements;
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for (ctrl_idx = 0; ctrl_idx < 2; ctrl_idx++) {
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isci_orom->ctrl[ctrl_idx].controller.mode_type = mode_type;
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isci_orom->ctrl[ctrl_idx].controller.max_concurrent_dev_spin_up =
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max_num_concurrent_dev_spin_up;
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isci_orom->ctrl[ctrl_idx].controller.do_enable_ssc =
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enable_ssc;
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for (port_idx = 0; port_idx < 4; port_idx++)
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isci_orom->ctrl[ctrl_idx].ports[port_idx].phy_mask =
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phy_mask[ctrl_idx][port_idx];
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for (phy_idx = 0; phy_idx < 4; phy_idx++) {
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].sas_address.high =
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(__u32)(sas_addr[ctrl_idx][phy_idx] >> 32);
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].sas_address.low =
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(__u32)(sas_addr[ctrl_idx][phy_idx]);
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control0 =
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afe_tx_amp_control0;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control1 =
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afe_tx_amp_control1;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control2 =
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afe_tx_amp_control2;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control3 =
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afe_tx_amp_control3;
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}
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}
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}
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int main(void)
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{
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int err;
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struct isci_orom *isci_orom;
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isci_orom = malloc(sizeof(struct isci_orom));
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memset(isci_orom, 0, sizeof(struct isci_orom));
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set_binary_values(isci_orom);
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err = write_blob(isci_orom);
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if (err < 0) {
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free(isci_orom);
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return err;
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}
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free(isci_orom);
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return 0;
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}
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@ -1,77 +0,0 @@
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#ifndef _CREATE_FW_H_
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#define _CREATE_FW_H_
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#include "../probe_roms.h"
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/* we are configuring for 2 SCUs */
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static const int num_elements = 2;
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/*
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* For all defined arrays:
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* elements 0-3 are for SCU0, ports 0-3
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* elements 4-7 are for SCU1, ports 0-3
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*
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* valid configurations for one SCU are:
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* P0 P1 P2 P3
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* ----------------
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* 0xF,0x0,0x0,0x0 # 1 x4 port
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* 0x3,0x0,0x4,0x8 # Phys 0 and 1 are a x2 port, phy 2 and phy 3 are each x1
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* # ports
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* 0x1,0x2,0xC,0x0 # Phys 0 and 1 are each x1 ports, phy 2 and phy 3 are a x2
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* # port
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* 0x3,0x0,0xC,0x0 # Phys 0 and 1 are a x2 port, phy 2 and phy 3 are a x2 port
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* 0x1,0x2,0x4,0x8 # Each phy is a x1 port (this is the default configuration)
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*
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* if there is a port/phy on which you do not wish to override the default
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* values, use the value assigned to UNINIT_PARAM (255).
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*/
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/* discovery mode type (port auto config mode by default ) */
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/*
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* if there is a port/phy on which you do not wish to override the default
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* values, use the value "0000000000000000". SAS address of zero's is
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* considered invalid and will not be used.
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*/
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#ifdef MPC
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static const int mode_type = SCIC_PORT_MANUAL_CONFIGURATION_MODE;
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static const __u8 phy_mask[2][4] = { {1, 2, 4, 8},
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{1, 2, 4, 8} };
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static const unsigned long long sas_addr[2][4] = { { 0x5FCFFFFFF0000001ULL,
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0x5FCFFFFFF0000002ULL,
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0x5FCFFFFFF0000003ULL,
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0x5FCFFFFFF0000004ULL },
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{ 0x5FCFFFFFF0000005ULL,
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0x5FCFFFFFF0000006ULL,
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0x5FCFFFFFF0000007ULL,
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0x5FCFFFFFF0000008ULL } };
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#else /* APC (default) */
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static const int mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
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static const __u8 phy_mask[2][4];
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static const unsigned long long sas_addr[2][4] = { { 0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL },
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{ 0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL } };
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#endif
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/* Maximum number of concurrent device spin up */
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static const int max_num_concurrent_dev_spin_up = 1;
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/* enable of ssc operation */
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static const int enable_ssc;
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/* AFE_TX_AMP_CONTROL */
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static const unsigned int afe_tx_amp_control0 = 0x000bdd08;
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static const unsigned int afe_tx_amp_control1 = 0x000ffc00;
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static const unsigned int afe_tx_amp_control2 = 0x000b7c09;
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static const unsigned int afe_tx_amp_control3 = 0x000afc6e;
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static const char blob_name[] = "isci_firmware.bin";
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static const char sig[] = "ISCUOEMB";
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static const unsigned char version = 0x10;
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#endif
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@ -82,7 +82,6 @@ fw-shipped-$(CONFIG_SERIAL_8250_CS) += cis/MT5634ZLX.cis cis/RS-COM-2P.cis \
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fw-shipped-$(CONFIG_PCMCIA_SMC91C92) += ositech/Xilinx7OD.bin
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fw-shipped-$(CONFIG_SCSI_ADVANSYS) += advansys/mcode.bin advansys/38C1600.bin \
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advansys/3550.bin advansys/38C0800.bin
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fw-shipped-$(CONFIG_SCSI_ISCI) += isci/isci_firmware.bin
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fw-shipped-$(CONFIG_SCSI_QLOGIC_1280) += qlogic/1040.bin qlogic/1280.bin \
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qlogic/12160.bin
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fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin
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@ -1,16 +0,0 @@
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:10000000495343554F454D42E80018100002000087
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:1000100000000000000000000101000000000000DE
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:10002000FFFFCF5F0100000008DD0B0000FC0F00A8
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:10003000097C0B006EFC0A00FFFFCF5F010000008F
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:1000400008DD0B0000FC0F00097C0B006EFC0A00B1
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:10005000FFFFCF5F0100000008DD0B0000FC0F0078
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:10006000097C0B006EFC0A00FFFFCF5F010000005F
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:1000700008DD0B0000FC0F00097C0B006EFC0A0081
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:100080000101000000000000FFFFCF5F0200000040
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:1000900008DD0B0000FC0F00097C0B006EFC0A0061
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:1000A000FFFFCF5F0200000008DD0B0000FC0F0027
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:1000B000097C0B006EFC0A00FFFFCF5F020000000E
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:1000C00008DD0B0000FC0F00097C0B006EFC0A0031
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:1000D000FFFFCF5F0200000008DD0B0000FC0F00F7
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:0800E000097C0B006EFC0A0014
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:00000001FF
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