dmaengine: add OMAP DMA engine driver
Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
571fa74034
commit
7bedaa5537
4 changed files with 553 additions and 0 deletions
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@ -261,6 +261,12 @@ config DMA_SA11X0
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SA-1110 SoCs. This DMA engine can only be used with on-chip
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SA-1110 SoCs. This DMA engine can only be used with on-chip
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devices.
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devices.
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config DMA_OMAP
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tristate "OMAP DMA support"
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depends on ARCH_OMAP
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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config DMA_ENGINE
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config DMA_ENGINE
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bool
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bool
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@ -29,3 +29,4 @@ obj-$(CONFIG_PCH_DMA) += pch_dma.o
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obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
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obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
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obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
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obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
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obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
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obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
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obj-$(CONFIG_DMA_OMAP) += omap-dma.o
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524
drivers/dma/omap-dma.c
Normal file
524
drivers/dma/omap-dma.c
Normal file
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@ -0,0 +1,524 @@
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/*
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* OMAP DMAengine support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/omap-dma.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "virt-dma.h"
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#include <plat/dma.h>
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struct omap_dmadev {
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struct dma_device ddev;
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spinlock_t lock;
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struct tasklet_struct task;
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struct list_head pending;
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};
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struct omap_chan {
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struct virt_dma_chan vc;
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struct list_head node;
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struct dma_slave_config cfg;
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unsigned dma_sig;
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int dma_ch;
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struct omap_desc *desc;
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unsigned sgidx;
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};
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struct omap_sg {
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dma_addr_t addr;
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uint32_t en; /* number of elements (24-bit) */
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uint32_t fn; /* number of frames (16-bit) */
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};
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struct omap_desc {
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struct virt_dma_desc vd;
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enum dma_transfer_direction dir;
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dma_addr_t dev_addr;
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uint8_t es; /* OMAP_DMA_DATA_TYPE_xxx */
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uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */
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uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */
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uint8_t periph_port; /* Peripheral port */
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unsigned sglen;
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struct omap_sg sg[0];
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};
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static const unsigned es_bytes[] = {
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[OMAP_DMA_DATA_TYPE_S8] = 1,
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[OMAP_DMA_DATA_TYPE_S16] = 2,
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[OMAP_DMA_DATA_TYPE_S32] = 4,
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};
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static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
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{
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return container_of(d, struct omap_dmadev, ddev);
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}
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static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
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{
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return container_of(c, struct omap_chan, vc.chan);
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}
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static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
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{
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return container_of(t, struct omap_desc, vd.tx);
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}
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static void omap_dma_desc_free(struct virt_dma_desc *vd)
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{
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kfree(container_of(vd, struct omap_desc, vd));
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}
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static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
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unsigned idx)
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{
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struct omap_sg *sg = d->sg + idx;
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if (d->dir == DMA_DEV_TO_MEM)
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omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
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OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
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else
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omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
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OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
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omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn,
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d->sync_mode, c->dma_sig, d->sync_type);
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omap_start_dma(c->dma_ch);
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}
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static void omap_dma_start_desc(struct omap_chan *c)
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{
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struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
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struct omap_desc *d;
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if (!vd) {
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c->desc = NULL;
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return;
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}
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list_del(&vd->node);
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c->desc = d = to_omap_dma_desc(&vd->tx);
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c->sgidx = 0;
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if (d->dir == DMA_DEV_TO_MEM)
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omap_set_dma_src_params(c->dma_ch, d->periph_port,
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OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, 0);
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else
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omap_set_dma_dest_params(c->dma_ch, d->periph_port,
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OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, 0);
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omap_dma_start_sg(c, d, 0);
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}
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static void omap_dma_callback(int ch, u16 status, void *data)
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{
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struct omap_chan *c = data;
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struct omap_desc *d;
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unsigned long flags;
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spin_lock_irqsave(&c->vc.lock, flags);
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d = c->desc;
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if (d) {
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if (++c->sgidx < d->sglen) {
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omap_dma_start_sg(c, d, c->sgidx);
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} else {
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omap_dma_start_desc(c);
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vchan_cookie_complete(&d->vd);
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}
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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}
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/*
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* This callback schedules all pending channels. We could be more
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* clever here by postponing allocation of the real DMA channels to
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* this point, and freeing them when our virtual channel becomes idle.
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*
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* We would then need to deal with 'all channels in-use'
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*/
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static void omap_dma_sched(unsigned long data)
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{
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struct omap_dmadev *d = (struct omap_dmadev *)data;
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LIST_HEAD(head);
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spin_lock_irq(&d->lock);
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list_splice_tail_init(&d->pending, &head);
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spin_unlock_irq(&d->lock);
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while (!list_empty(&head)) {
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struct omap_chan *c = list_first_entry(&head,
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struct omap_chan, node);
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spin_lock_irq(&c->vc.lock);
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list_del_init(&c->node);
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omap_dma_start_desc(c);
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spin_unlock_irq(&c->vc.lock);
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}
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}
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static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct omap_chan *c = to_omap_dma_chan(chan);
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dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);
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return omap_request_dma(c->dma_sig, "DMA engine",
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omap_dma_callback, c, &c->dma_ch);
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}
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static void omap_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct omap_chan *c = to_omap_dma_chan(chan);
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vchan_free_chan_resources(&c->vc);
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omap_free_dma(c->dma_ch);
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dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
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}
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static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *txstate)
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{
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/*
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* FIXME: do we need to return pending bytes?
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* We have no users of that info at the moment...
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*/
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return dma_cookie_status(chan, cookie, txstate);
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}
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static void omap_dma_issue_pending(struct dma_chan *chan)
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{
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struct omap_chan *c = to_omap_dma_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&c->vc.lock, flags);
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if (vchan_issue_pending(&c->vc) && !c->desc) {
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struct omap_dmadev *d = to_omap_dma_dev(chan->device);
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spin_lock(&d->lock);
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if (list_empty(&c->node))
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list_add_tail(&c->node, &d->pending);
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spin_unlock(&d->lock);
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tasklet_schedule(&d->task);
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}
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spin_unlock_irqrestore(&c->vc.lock, flags);
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}
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static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
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enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
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{
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struct omap_chan *c = to_omap_dma_chan(chan);
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enum dma_slave_buswidth dev_width;
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struct scatterlist *sgent;
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struct omap_desc *d;
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dma_addr_t dev_addr;
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unsigned i, j = 0, es, en, frame_bytes, sync_type;
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u32 burst;
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if (dir == DMA_DEV_TO_MEM) {
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dev_addr = c->cfg.src_addr;
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dev_width = c->cfg.src_addr_width;
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burst = c->cfg.src_maxburst;
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sync_type = OMAP_DMA_SRC_SYNC;
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} else if (dir == DMA_MEM_TO_DEV) {
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dev_addr = c->cfg.dst_addr;
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dev_width = c->cfg.dst_addr_width;
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burst = c->cfg.dst_maxburst;
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sync_type = OMAP_DMA_DST_SYNC;
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} else {
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dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
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return NULL;
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}
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/* Bus width translates to the element size (ES) */
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switch (dev_width) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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es = OMAP_DMA_DATA_TYPE_S8;
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break;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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es = OMAP_DMA_DATA_TYPE_S16;
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break;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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es = OMAP_DMA_DATA_TYPE_S32;
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break;
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default: /* not reached */
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return NULL;
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}
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/* Now allocate and setup the descriptor. */
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d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
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if (!d)
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return NULL;
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d->dir = dir;
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d->dev_addr = dev_addr;
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d->es = es;
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d->sync_mode = OMAP_DMA_SYNC_FRAME;
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d->sync_type = sync_type;
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d->periph_port = OMAP_DMA_PORT_TIPB;
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/*
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* Build our scatterlist entries: each contains the address,
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* the number of elements (EN) in each frame, and the number of
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* frames (FN). Number of bytes for this entry = ES * EN * FN.
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*
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* Burst size translates to number of elements with frame sync.
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* Note: DMA engine defines burst to be the number of dev-width
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* transfers.
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*/
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en = burst;
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frame_bytes = es_bytes[es] * en;
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for_each_sg(sgl, sgent, sglen, i) {
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d->sg[j].addr = sg_dma_address(sgent);
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d->sg[j].en = en;
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d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
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j++;
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}
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d->sglen = j;
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return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
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}
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static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg)
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{
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if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
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cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
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return -EINVAL;
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memcpy(&c->cfg, cfg, sizeof(c->cfg));
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return 0;
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}
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static int omap_dma_terminate_all(struct omap_chan *c)
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{
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struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&c->vc.lock, flags);
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/* Prevent this channel being scheduled */
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spin_lock(&d->lock);
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list_del_init(&c->node);
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spin_unlock(&d->lock);
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/*
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* Stop DMA activity: we assume the callback will not be called
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* after omap_stop_dma() returns (even if it does, it will see
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* c->desc is NULL and exit.)
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*/
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if (c->desc) {
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c->desc = NULL;
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omap_stop_dma(c->dma_ch);
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}
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vchan_get_all_descriptors(&c->vc, &head);
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spin_unlock_irqrestore(&c->vc.lock, flags);
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vchan_dma_desc_free_list(&c->vc, &head);
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return 0;
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}
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static int omap_dma_pause(struct omap_chan *c)
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{
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/* FIXME: not supported by platform private API */
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return -EINVAL;
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}
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static int omap_dma_resume(struct omap_chan *c)
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{
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/* FIXME: not supported by platform private API */
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
||||||
|
unsigned long arg)
|
||||||
|
{
|
||||||
|
struct omap_chan *c = to_omap_dma_chan(chan);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
switch (cmd) {
|
||||||
|
case DMA_SLAVE_CONFIG:
|
||||||
|
ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case DMA_TERMINATE_ALL:
|
||||||
|
ret = omap_dma_terminate_all(c);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case DMA_PAUSE:
|
||||||
|
ret = omap_dma_pause(c);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case DMA_RESUME:
|
||||||
|
ret = omap_dma_resume(c);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
ret = -ENXIO;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
|
||||||
|
{
|
||||||
|
struct omap_chan *c;
|
||||||
|
|
||||||
|
c = kzalloc(sizeof(*c), GFP_KERNEL);
|
||||||
|
if (!c)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
c->dma_sig = dma_sig;
|
||||||
|
c->vc.desc_free = omap_dma_desc_free;
|
||||||
|
vchan_init(&c->vc, &od->ddev);
|
||||||
|
INIT_LIST_HEAD(&c->node);
|
||||||
|
|
||||||
|
od->ddev.chancnt++;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void omap_dma_free(struct omap_dmadev *od)
|
||||||
|
{
|
||||||
|
tasklet_kill(&od->task);
|
||||||
|
while (!list_empty(&od->ddev.channels)) {
|
||||||
|
struct omap_chan *c = list_first_entry(&od->ddev.channels,
|
||||||
|
struct omap_chan, vc.chan.device_node);
|
||||||
|
|
||||||
|
list_del(&c->vc.chan.device_node);
|
||||||
|
tasklet_kill(&c->vc.task);
|
||||||
|
kfree(c);
|
||||||
|
}
|
||||||
|
kfree(od);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int omap_dma_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct omap_dmadev *od;
|
||||||
|
int rc, i;
|
||||||
|
|
||||||
|
od = kzalloc(sizeof(*od), GFP_KERNEL);
|
||||||
|
if (!od)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
|
||||||
|
od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
|
||||||
|
od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
|
||||||
|
od->ddev.device_tx_status = omap_dma_tx_status;
|
||||||
|
od->ddev.device_issue_pending = omap_dma_issue_pending;
|
||||||
|
od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
|
||||||
|
od->ddev.device_control = omap_dma_control;
|
||||||
|
od->ddev.dev = &pdev->dev;
|
||||||
|
INIT_LIST_HEAD(&od->ddev.channels);
|
||||||
|
INIT_LIST_HEAD(&od->pending);
|
||||||
|
spin_lock_init(&od->lock);
|
||||||
|
|
||||||
|
tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
|
||||||
|
|
||||||
|
for (i = 0; i < 127; i++) {
|
||||||
|
rc = omap_dma_chan_init(od, i);
|
||||||
|
if (rc) {
|
||||||
|
omap_dma_free(od);
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
rc = dma_async_device_register(&od->ddev);
|
||||||
|
if (rc) {
|
||||||
|
pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
|
||||||
|
rc);
|
||||||
|
omap_dma_free(od);
|
||||||
|
} else {
|
||||||
|
platform_set_drvdata(pdev, od);
|
||||||
|
}
|
||||||
|
|
||||||
|
dev_info(&pdev->dev, "OMAP DMA engine driver\n");
|
||||||
|
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int omap_dma_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct omap_dmadev *od = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
dma_async_device_unregister(&od->ddev);
|
||||||
|
omap_dma_free(od);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct platform_driver omap_dma_driver = {
|
||||||
|
.probe = omap_dma_probe,
|
||||||
|
.remove = omap_dma_remove,
|
||||||
|
.driver = {
|
||||||
|
.name = "omap-dma-engine",
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
|
||||||
|
{
|
||||||
|
if (chan->device->dev->driver == &omap_dma_driver.driver) {
|
||||||
|
struct omap_chan *c = to_omap_dma_chan(chan);
|
||||||
|
unsigned req = *(unsigned *)param;
|
||||||
|
|
||||||
|
return req == c->dma_sig;
|
||||||
|
}
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
|
||||||
|
|
||||||
|
static struct platform_device *pdev;
|
||||||
|
|
||||||
|
static const struct platform_device_info omap_dma_dev_info = {
|
||||||
|
.name = "omap-dma-engine",
|
||||||
|
.id = -1,
|
||||||
|
.dma_mask = DMA_BIT_MASK(32),
|
||||||
|
};
|
||||||
|
|
||||||
|
static int omap_dma_init(void)
|
||||||
|
{
|
||||||
|
int rc = platform_driver_register(&omap_dma_driver);
|
||||||
|
|
||||||
|
if (rc == 0) {
|
||||||
|
pdev = platform_device_register_full(&omap_dma_dev_info);
|
||||||
|
if (IS_ERR(pdev)) {
|
||||||
|
platform_driver_unregister(&omap_dma_driver);
|
||||||
|
rc = PTR_ERR(pdev);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
subsys_initcall(omap_dma_init);
|
||||||
|
|
||||||
|
static void __exit omap_dma_exit(void)
|
||||||
|
{
|
||||||
|
platform_device_unregister(pdev);
|
||||||
|
platform_driver_unregister(&omap_dma_driver);
|
||||||
|
}
|
||||||
|
module_exit(omap_dma_exit);
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Russell King");
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
22
include/linux/omap-dma.h
Normal file
22
include/linux/omap-dma.h
Normal file
|
|
@ -0,0 +1,22 @@
|
||||||
|
/*
|
||||||
|
* OMAP DMA Engine support
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
#ifndef __LINUX_OMAP_DMA_H
|
||||||
|
#define __LINUX_OMAP_DMA_H
|
||||||
|
|
||||||
|
struct dma_chan;
|
||||||
|
|
||||||
|
#if defined(CONFIG_DMA_OMAP) || defined(CONFIG_DMA_OMAP_MODULE)
|
||||||
|
bool omap_dma_filter_fn(struct dma_chan *, void *);
|
||||||
|
#else
|
||||||
|
static inline bool omap_dma_filter_fn(struct dma_chan *c, void *d)
|
||||||
|
{
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Add table
Add a link
Reference in a new issue