regmap: irq: add support for chips who have separate unmask registers
Some chips have separate unmask registers from mask registers for some consideration of concurrency SMP write performance. And this patch adds a flag for it. An user will be CSR SiRFSoC ARM chips. Signed-off-by: Guo Zeng <Guo.Zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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2 changed files with 31 additions and 3 deletions
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@ -800,6 +800,8 @@ struct regmap_irq {
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*
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* @status_base: Base status register address.
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* @mask_base: Base mask register address.
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* @unmask_base: Base unmask register address. for chips who have
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* separate mask and unmask registers
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* @ack_base: Base ack address. If zero then the chip is clear on read.
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* Using zero value is possible with @use_ack bit.
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* @wake_base: Base address for wake enables. If zero unsupported.
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@ -820,6 +822,7 @@ struct regmap_irq_chip {
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unsigned int status_base;
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unsigned int mask_base;
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unsigned int unmask_base;
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unsigned int ack_base;
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unsigned int wake_base;
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unsigned int irq_reg_stride;
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