Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (58 commits) mfd: Add twl6030 regulator subdevices regulator: Add support for twl6030 regulators rtc: Add twl6030 RTC support mfd: Add support for twl6030 irq framework mfd: Rename twl4030_ routines in twl-regulator.c mfd: Rename twl4030_ routines in rtc-twl.c mfd: Rename all twl4030_i2c* mfd: Rename twl4030* driver files to enable re-use mfd: Clarify twl4030 return value for read and write mfd: Add all twl4030 regulators to the twl4030 mfd driver mfd: Don't set mc13783 ADREFMODE for touch conversions mfd: Remove ezx-pcap defines for custom led gpio encoding mfd: Near complete mc13783 rewrite mfd: Remove build time warning for WM835x register default tables mfd: Force I2C to be built in when building WM831x mfd: Don't allow wm831x to be built as a module mfd: Fix incorrect error check for wm8350-core mfd: Fix twl4030 warning gpiolib: Implement gpio_to_irq() for wm831x mfd: Remove default selection of AB4500 ...
This commit is contained in:
Linus Torvalds
commit
76b8f82cde
69 changed files with 5237 additions and 2135 deletions
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@ -72,6 +72,21 @@
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|||
#define TPS_VDCDC1 0x0c
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# define TPS_ENABLE_LP (1 << 3)
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#define TPS_VDCDC2 0x0d
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# define TPS_LP_COREOFF (1 << 7)
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# define TPS_VCORE_1_8V (7<<4)
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# define TPS_VCORE_1_5V (6 << 4)
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# define TPS_VCORE_1_4V (5 << 4)
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# define TPS_VCORE_1_3V (4 << 4)
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# define TPS_VCORE_1_2V (3 << 4)
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# define TPS_VCORE_1_1V (2 << 4)
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# define TPS_VCORE_1_0V (1 << 4)
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# define TPS_VCORE_0_85V (0 << 4)
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# define TPS_VCORE_LP_1_2V (3 << 2)
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# define TPS_VCORE_LP_1_1V (2 << 2)
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# define TPS_VCORE_LP_1_0V (1 << 2)
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# define TPS_VCORE_LP_0_85V (0 << 2)
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# define TPS_VIB (1 << 1)
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# define TPS_VCORE_DISCH (1 << 0)
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#define TPS_VREGS1 0x0e
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# define TPS_LDO2_ENABLE (1 << 7)
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# define TPS_LDO2_OFF (1 << 6)
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@ -152,6 +167,10 @@ extern int tps65010_config_vregs1(unsigned value);
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*/
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extern int tps65013_set_low_pwr(unsigned mode);
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/* tps65010_set_vdcdc2
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* value to be written to VDCDC2
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*/
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extern int tps65010_config_vdcdc2(unsigned value);
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struct i2c_client;
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@ -22,8 +22,8 @@
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*
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*/
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#ifndef __TWL4030_H_
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#define __TWL4030_H_
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#ifndef __TWL_H_
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#define __TWL_H_
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#include <linux/types.h>
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#include <linux/input/matrix_keypad.h>
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@ -61,28 +61,112 @@
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#define TWL4030_MODULE_PWMA 0x0E
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#define TWL4030_MODULE_PWMB 0x0F
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#define TWL5031_MODULE_ACCESSORY 0x10
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#define TWL5031_MODULE_INTERRUPTS 0x11
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/* Slave 3 (i2c address 0x4b) */
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#define TWL4030_MODULE_BACKUP 0x10
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#define TWL4030_MODULE_INT 0x11
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#define TWL4030_MODULE_PM_MASTER 0x12
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#define TWL4030_MODULE_PM_RECEIVER 0x13
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#define TWL4030_MODULE_RTC 0x14
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#define TWL4030_MODULE_SECURED_REG 0x15
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#define TWL4030_MODULE_BACKUP 0x12
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#define TWL4030_MODULE_INT 0x13
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#define TWL4030_MODULE_PM_MASTER 0x14
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#define TWL4030_MODULE_PM_RECEIVER 0x15
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#define TWL4030_MODULE_RTC 0x16
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#define TWL4030_MODULE_SECURED_REG 0x17
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#define TWL_MODULE_USB TWL4030_MODULE_USB
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#define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE
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#define TWL_MODULE_PIH TWL4030_MODULE_PIH
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#define TWL_MODULE_MADC TWL4030_MODULE_MADC
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#define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE
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#define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
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#define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
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#define TWL_MODULE_RTC TWL4030_MODULE_RTC
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#define GPIO_INTR_OFFSET 0
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#define KEYPAD_INTR_OFFSET 1
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#define BCI_INTR_OFFSET 2
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#define MADC_INTR_OFFSET 3
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#define USB_INTR_OFFSET 4
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#define BCI_PRES_INTR_OFFSET 9
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#define USB_PRES_INTR_OFFSET 10
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#define RTC_INTR_OFFSET 11
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/*
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* Offset from TWL6030_IRQ_BASE / pdata->irq_base
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*/
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#define PWR_INTR_OFFSET 0
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#define HOTDIE_INTR_OFFSET 12
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#define SMPSLDO_INTR_OFFSET 13
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#define BATDETECT_INTR_OFFSET 14
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#define SIMDETECT_INTR_OFFSET 15
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#define MMCDETECT_INTR_OFFSET 16
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#define GASGAUGE_INTR_OFFSET 17
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#define USBOTG_INTR_OFFSET 4
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#define CHARGER_INTR_OFFSET 2
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#define RSV_INTR_OFFSET 0
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/* INT register offsets */
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#define REG_INT_STS_A 0x00
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#define REG_INT_STS_B 0x01
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#define REG_INT_STS_C 0x02
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#define REG_INT_MSK_LINE_A 0x03
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#define REG_INT_MSK_LINE_B 0x04
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#define REG_INT_MSK_LINE_C 0x05
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#define REG_INT_MSK_STS_A 0x06
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#define REG_INT_MSK_STS_B 0x07
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#define REG_INT_MSK_STS_C 0x08
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/* MASK INT REG GROUP A */
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#define TWL6030_PWR_INT_MASK 0x07
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#define TWL6030_RTC_INT_MASK 0x18
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#define TWL6030_HOTDIE_INT_MASK 0x20
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#define TWL6030_SMPSLDOA_INT_MASK 0xC0
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/* MASK INT REG GROUP B */
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#define TWL6030_SMPSLDOB_INT_MASK 0x01
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#define TWL6030_BATDETECT_INT_MASK 0x02
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#define TWL6030_SIMDETECT_INT_MASK 0x04
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#define TWL6030_MMCDETECT_INT_MASK 0x08
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#define TWL6030_GPADC_INT_MASK 0x60
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#define TWL6030_GASGAUGE_INT_MASK 0x80
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/* MASK INT REG GROUP C */
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#define TWL6030_USBOTG_INT_MASK 0x0F
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#define TWL6030_CHARGER_CTRL_INT_MASK 0x10
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#define TWL6030_CHARGER_FAULT_INT_MASK 0x60
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#define TWL4030_CLASS_ID 0x4030
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#define TWL6030_CLASS_ID 0x6030
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unsigned int twl_rev(void);
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#define GET_TWL_REV (twl_rev())
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#define TWL_CLASS_IS(class, id) \
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static inline int twl_class_is_ ##class(void) \
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{ \
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return ((id) == (GET_TWL_REV)) ? 1 : 0; \
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}
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TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
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TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
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/*
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* Read and write single 8-bit registers
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*/
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int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
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int twl4030_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
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int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
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int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
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/*
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* Read and write several 8-bit registers at once.
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*
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* IMPORTANT: For twl4030_i2c_write(), allocate num_bytes + 1
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* IMPORTANT: For twl_i2c_write(), allocate num_bytes + 1
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* for the value, and populate your data starting at offset 1.
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*/
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int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
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int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
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/*----------------------------------------------------------------------*/
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@ -221,6 +305,38 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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/*----------------------------------------------------------------------*/
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/*
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* Accessory Interrupts
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*/
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#define TWL5031_ACIIMR_LSB 0x05
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#define TWL5031_ACIIMR_MSB 0x06
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#define TWL5031_ACIIDR_LSB 0x07
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#define TWL5031_ACIIDR_MSB 0x08
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#define TWL5031_ACCISR1 0x0F
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#define TWL5031_ACCIMR1 0x10
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#define TWL5031_ACCISR2 0x11
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#define TWL5031_ACCIMR2 0x12
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#define TWL5031_ACCSIR 0x13
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#define TWL5031_ACCEDR1 0x14
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#define TWL5031_ACCSIHCTRL 0x15
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/*----------------------------------------------------------------------*/
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/*
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* Battery Charger Controller
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*/
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#define TWL5031_INTERRUPTS_BCIISR1 0x0
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#define TWL5031_INTERRUPTS_BCIIMR1 0x1
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#define TWL5031_INTERRUPTS_BCIISR2 0x2
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#define TWL5031_INTERRUPTS_BCIIMR2 0x3
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#define TWL5031_INTERRUPTS_BCISIR 0x4
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#define TWL5031_INTERRUPTS_BCIEDR1 0x5
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#define TWL5031_INTERRUPTS_BCIEDR2 0x6
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#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
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/*----------------------------------------------------------------------*/
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/* Power bus message definitions */
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/* The TWL4030/5030 splits its power-management resources (the various
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@ -250,6 +366,7 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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#define RES_TYPE_ALL 0x7
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/* Resource states */
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#define RES_STATE_WRST 0xF
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#define RES_STATE_ACTIVE 0xE
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#define RES_STATE_SLEEP 0x8
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@ -310,8 +427,18 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
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#define MSG_SINGULAR(devgrp, id, state) \
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((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
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#define MSG_BROADCAST_ALL(devgrp, state) \
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((devgrp) << 5 | (state))
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#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
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#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
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#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
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/*----------------------------------------------------------------------*/
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struct twl4030_clock_init_data {
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bool ck32k_lowpwr_enable;
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};
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struct twl4030_bci_platform_data {
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int *battery_tmp_tbl;
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unsigned int tblsize;
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@ -391,12 +518,15 @@ struct twl4030_resconfig {
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u8 devgroup; /* Processor group that Power resource belongs to */
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u8 type; /* Power resource addressed, 6 / broadcast message */
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u8 type2; /* Power resource addressed, 3 / broadcast message */
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u8 remap_off; /* off state remapping */
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u8 remap_sleep; /* sleep state remapping */
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};
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struct twl4030_power_data {
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struct twl4030_script **scripts;
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unsigned num;
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struct twl4030_resconfig *resource_config;
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#define TWL4030_RESCONFIG_UNDEF ((u8)-1)
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};
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extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
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|
@ -421,6 +551,7 @@ struct twl4030_codec_data {
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struct twl4030_platform_data {
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unsigned irq_base, irq_end;
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struct twl4030_clock_init_data *clock;
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struct twl4030_bci_platform_data *bci;
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struct twl4030_gpio_platform_data *gpio;
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struct twl4030_madc_platform_data *madc;
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|
|
@ -429,19 +560,31 @@ struct twl4030_platform_data {
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struct twl4030_power_data *power;
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struct twl4030_codec_data *codec;
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|
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/* LDO regulators */
|
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/* Common LDO regulators for TWL4030/TWL6030 */
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struct regulator_init_data *vdac;
|
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struct regulator_init_data *vaux1;
|
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struct regulator_init_data *vaux2;
|
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struct regulator_init_data *vaux3;
|
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/* TWL4030 LDO regulators */
|
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struct regulator_init_data *vpll1;
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struct regulator_init_data *vpll2;
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struct regulator_init_data *vmmc1;
|
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struct regulator_init_data *vmmc2;
|
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struct regulator_init_data *vsim;
|
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struct regulator_init_data *vaux1;
|
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struct regulator_init_data *vaux2;
|
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struct regulator_init_data *vaux3;
|
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struct regulator_init_data *vaux4;
|
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|
||||
/* REVISIT more to come ... _nothing_ should be hard-wired */
|
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struct regulator_init_data *vio;
|
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struct regulator_init_data *vdd1;
|
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struct regulator_init_data *vdd2;
|
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struct regulator_init_data *vintana1;
|
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struct regulator_init_data *vintana2;
|
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struct regulator_init_data *vintdig;
|
||||
/* TWL6030 LDO regulators */
|
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struct regulator_init_data *vmmc;
|
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struct regulator_init_data *vpp;
|
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struct regulator_init_data *vusim;
|
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struct regulator_init_data *vana;
|
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struct regulator_init_data *vcxio;
|
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struct regulator_init_data *vusb;
|
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};
|
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|
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/*----------------------------------------------------------------------*/
|
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|
|
@ -473,6 +616,7 @@ int twl4030_sih_setup(int module);
|
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* VIO is generally fixed.
|
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*/
|
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|
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/* TWL4030 SMPS/LDO's */
|
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/* EXTERNAL dc-to-dc buck converters */
|
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#define TWL4030_REG_VDD1 0
|
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#define TWL4030_REG_VDD2 1
|
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|
|
@ -499,4 +643,31 @@ int twl4030_sih_setup(int module);
|
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#define TWL4030_REG_VUSB1V8 18
|
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#define TWL4030_REG_VUSB3V1 19
|
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|
||||
/* TWL6030 SMPS/LDO's */
|
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/* EXTERNAL dc-to-dc buck convertor contollable via SR */
|
||||
#define TWL6030_REG_VDD1 30
|
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#define TWL6030_REG_VDD2 31
|
||||
#define TWL6030_REG_VDD3 32
|
||||
|
||||
/* Non SR compliant dc-to-dc buck convertors */
|
||||
#define TWL6030_REG_VMEM 33
|
||||
#define TWL6030_REG_V2V1 34
|
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#define TWL6030_REG_V1V29 35
|
||||
#define TWL6030_REG_V1V8 36
|
||||
|
||||
/* EXTERNAL LDOs */
|
||||
#define TWL6030_REG_VAUX1_6030 37
|
||||
#define TWL6030_REG_VAUX2_6030 38
|
||||
#define TWL6030_REG_VAUX3_6030 39
|
||||
#define TWL6030_REG_VMMC 40
|
||||
#define TWL6030_REG_VPP 41
|
||||
#define TWL6030_REG_VUSIM 42
|
||||
#define TWL6030_REG_VANA 43
|
||||
#define TWL6030_REG_VCXIO 44
|
||||
#define TWL6030_REG_VDAC 45
|
||||
#define TWL6030_REG_VUSB 46
|
||||
|
||||
/* INTERNAL LDOs */
|
||||
#define TWL6030_REG_VRTC 47
|
||||
|
||||
#endif /* End of __TWL4030_H */
|
||||
217
include/linux/mfd/88pm8607.h
Normal file
217
include/linux/mfd/88pm8607.h
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* Marvell 88PM8607 Interface
|
||||
*
|
||||
* Copyright (C) 2009 Marvell International Ltd.
|
||||
* Haojian Zhuang <haojian.zhuang@marvell.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_88PM8607_H
|
||||
#define __LINUX_MFD_88PM8607_H
|
||||
|
||||
enum {
|
||||
PM8607_ID_BUCK1 = 0,
|
||||
PM8607_ID_BUCK2,
|
||||
PM8607_ID_BUCK3,
|
||||
|
||||
PM8607_ID_LDO1,
|
||||
PM8607_ID_LDO2,
|
||||
PM8607_ID_LDO3,
|
||||
PM8607_ID_LDO4,
|
||||
PM8607_ID_LDO5,
|
||||
PM8607_ID_LDO6,
|
||||
PM8607_ID_LDO7,
|
||||
PM8607_ID_LDO8,
|
||||
PM8607_ID_LDO9,
|
||||
PM8607_ID_LDO10,
|
||||
PM8607_ID_LDO12,
|
||||
PM8607_ID_LDO14,
|
||||
|
||||
PM8607_ID_RG_MAX,
|
||||
};
|
||||
|
||||
#define CHIP_ID (0x40)
|
||||
#define CHIP_ID_MASK (0xF8)
|
||||
|
||||
/* Interrupt Registers */
|
||||
#define PM8607_STATUS_1 (0x01)
|
||||
#define PM8607_STATUS_2 (0x02)
|
||||
#define PM8607_INT_STATUS1 (0x03)
|
||||
#define PM8607_INT_STATUS2 (0x04)
|
||||
#define PM8607_INT_STATUS3 (0x05)
|
||||
#define PM8607_INT_MASK_1 (0x06)
|
||||
#define PM8607_INT_MASK_2 (0x07)
|
||||
#define PM8607_INT_MASK_3 (0x08)
|
||||
|
||||
/* Regulator Control Registers */
|
||||
#define PM8607_LDO1 (0x10)
|
||||
#define PM8607_LDO2 (0x11)
|
||||
#define PM8607_LDO3 (0x12)
|
||||
#define PM8607_LDO4 (0x13)
|
||||
#define PM8607_LDO5 (0x14)
|
||||
#define PM8607_LDO6 (0x15)
|
||||
#define PM8607_LDO7 (0x16)
|
||||
#define PM8607_LDO8 (0x17)
|
||||
#define PM8607_LDO9 (0x18)
|
||||
#define PM8607_LDO10 (0x19)
|
||||
#define PM8607_LDO12 (0x1A)
|
||||
#define PM8607_LDO14 (0x1B)
|
||||
#define PM8607_SLEEP_MODE1 (0x1C)
|
||||
#define PM8607_SLEEP_MODE2 (0x1D)
|
||||
#define PM8607_SLEEP_MODE3 (0x1E)
|
||||
#define PM8607_SLEEP_MODE4 (0x1F)
|
||||
#define PM8607_GO (0x20)
|
||||
#define PM8607_SLEEP_BUCK1 (0x21)
|
||||
#define PM8607_SLEEP_BUCK2 (0x22)
|
||||
#define PM8607_SLEEP_BUCK3 (0x23)
|
||||
#define PM8607_BUCK1 (0x24)
|
||||
#define PM8607_BUCK2 (0x25)
|
||||
#define PM8607_BUCK3 (0x26)
|
||||
#define PM8607_BUCK_CONTROLS (0x27)
|
||||
#define PM8607_SUPPLIES_EN11 (0x2B)
|
||||
#define PM8607_SUPPLIES_EN12 (0x2C)
|
||||
#define PM8607_GROUP1 (0x2D)
|
||||
#define PM8607_GROUP2 (0x2E)
|
||||
#define PM8607_GROUP3 (0x2F)
|
||||
#define PM8607_GROUP4 (0x30)
|
||||
#define PM8607_GROUP5 (0x31)
|
||||
#define PM8607_GROUP6 (0x32)
|
||||
#define PM8607_SUPPLIES_EN21 (0x33)
|
||||
#define PM8607_SUPPLIES_EN22 (0x34)
|
||||
|
||||
/* RTC Control Registers */
|
||||
#define PM8607_RTC1 (0xA0)
|
||||
#define PM8607_RTC_COUNTER1 (0xA1)
|
||||
#define PM8607_RTC_COUNTER2 (0xA2)
|
||||
#define PM8607_RTC_COUNTER3 (0xA3)
|
||||
#define PM8607_RTC_COUNTER4 (0xA4)
|
||||
#define PM8607_RTC_EXPIRE1 (0xA5)
|
||||
#define PM8607_RTC_EXPIRE2 (0xA6)
|
||||
#define PM8607_RTC_EXPIRE3 (0xA7)
|
||||
#define PM8607_RTC_EXPIRE4 (0xA8)
|
||||
#define PM8607_RTC_TRIM1 (0xA9)
|
||||
#define PM8607_RTC_TRIM2 (0xAA)
|
||||
#define PM8607_RTC_TRIM3 (0xAB)
|
||||
#define PM8607_RTC_TRIM4 (0xAC)
|
||||
#define PM8607_RTC_MISC1 (0xAD)
|
||||
#define PM8607_RTC_MISC2 (0xAE)
|
||||
#define PM8607_RTC_MISC3 (0xAF)
|
||||
|
||||
/* Misc Registers */
|
||||
#define PM8607_CHIP_ID (0x00)
|
||||
#define PM8607_LDO1 (0x10)
|
||||
#define PM8607_DVC3 (0x26)
|
||||
#define PM8607_MISC1 (0x40)
|
||||
|
||||
/* bit definitions for PM8607 events */
|
||||
#define PM8607_EVENT_ONKEY (1 << 0)
|
||||
#define PM8607_EVENT_EXTON (1 << 1)
|
||||
#define PM8607_EVENT_CHG (1 << 2)
|
||||
#define PM8607_EVENT_BAT (1 << 3)
|
||||
#define PM8607_EVENT_RTC (1 << 4)
|
||||
#define PM8607_EVENT_CC (1 << 5)
|
||||
#define PM8607_EVENT_VBAT (1 << 8)
|
||||
#define PM8607_EVENT_VCHG (1 << 9)
|
||||
#define PM8607_EVENT_VSYS (1 << 10)
|
||||
#define PM8607_EVENT_TINT (1 << 11)
|
||||
#define PM8607_EVENT_GPADC0 (1 << 12)
|
||||
#define PM8607_EVENT_GPADC1 (1 << 13)
|
||||
#define PM8607_EVENT_GPADC2 (1 << 14)
|
||||
#define PM8607_EVENT_GPADC3 (1 << 15)
|
||||
#define PM8607_EVENT_AUDIO_SHORT (1 << 16)
|
||||
#define PM8607_EVENT_PEN (1 << 17)
|
||||
#define PM8607_EVENT_HEADSET (1 << 18)
|
||||
#define PM8607_EVENT_HOOK (1 << 19)
|
||||
#define PM8607_EVENT_MICIN (1 << 20)
|
||||
#define PM8607_EVENT_CHG_TIMEOUT (1 << 21)
|
||||
#define PM8607_EVENT_CHG_DONE (1 << 22)
|
||||
#define PM8607_EVENT_CHG_FAULT (1 << 23)
|
||||
|
||||
/* bit definitions of Status Query Interface */
|
||||
#define PM8607_STATUS_CC (1 << 3)
|
||||
#define PM8607_STATUS_PEN (1 << 4)
|
||||
#define PM8607_STATUS_HEADSET (1 << 5)
|
||||
#define PM8607_STATUS_HOOK (1 << 6)
|
||||
#define PM8607_STATUS_MICIN (1 << 7)
|
||||
#define PM8607_STATUS_ONKEY (1 << 8)
|
||||
#define PM8607_STATUS_EXTON (1 << 9)
|
||||
#define PM8607_STATUS_CHG (1 << 10)
|
||||
#define PM8607_STATUS_BAT (1 << 11)
|
||||
#define PM8607_STATUS_VBUS (1 << 12)
|
||||
#define PM8607_STATUS_OV (1 << 13)
|
||||
|
||||
/* bit definitions of BUCK3 */
|
||||
#define PM8607_BUCK3_DOUBLE (1 << 6)
|
||||
|
||||
/* bit definitions of Misc1 */
|
||||
#define PM8607_MISC1_PI2C (1 << 0)
|
||||
|
||||
/* Interrupt Number in 88PM8607 */
|
||||
enum {
|
||||
PM8607_IRQ_ONKEY = 0,
|
||||
PM8607_IRQ_EXTON,
|
||||
PM8607_IRQ_CHG,
|
||||
PM8607_IRQ_BAT,
|
||||
PM8607_IRQ_RTC,
|
||||
PM8607_IRQ_VBAT = 8,
|
||||
PM8607_IRQ_VCHG,
|
||||
PM8607_IRQ_VSYS,
|
||||
PM8607_IRQ_TINT,
|
||||
PM8607_IRQ_GPADC0,
|
||||
PM8607_IRQ_GPADC1,
|
||||
PM8607_IRQ_GPADC2,
|
||||
PM8607_IRQ_GPADC3,
|
||||
PM8607_IRQ_AUDIO_SHORT = 16,
|
||||
PM8607_IRQ_PEN,
|
||||
PM8607_IRQ_HEADSET,
|
||||
PM8607_IRQ_HOOK,
|
||||
PM8607_IRQ_MICIN,
|
||||
PM8607_IRQ_CHG_FAIL,
|
||||
PM8607_IRQ_CHG_DONE,
|
||||
PM8607_IRQ_CHG_FAULT,
|
||||
};
|
||||
|
||||
enum {
|
||||
PM8607_CHIP_A0 = 0x40,
|
||||
PM8607_CHIP_A1 = 0x41,
|
||||
PM8607_CHIP_B0 = 0x48,
|
||||
};
|
||||
|
||||
|
||||
struct pm8607_chip {
|
||||
struct device *dev;
|
||||
struct mutex io_lock;
|
||||
struct i2c_client *client;
|
||||
|
||||
int (*read)(struct pm8607_chip *chip, int reg, int bytes, void *dest);
|
||||
int (*write)(struct pm8607_chip *chip, int reg, int bytes, void *src);
|
||||
|
||||
int buck3_double; /* DVC ramp slope double */
|
||||
unsigned char chip_id;
|
||||
|
||||
};
|
||||
|
||||
#define PM8607_MAX_REGULATOR 15 /* 3 Bucks, 12 LDOs */
|
||||
|
||||
enum {
|
||||
GI2C_PORT = 0,
|
||||
PI2C_PORT,
|
||||
};
|
||||
|
||||
struct pm8607_platform_data {
|
||||
int i2c_port; /* Controlled by GI2C or PI2C */
|
||||
struct regulator_init_data *regulator[PM8607_MAX_REGULATOR];
|
||||
};
|
||||
|
||||
extern int pm8607_reg_read(struct pm8607_chip *, int);
|
||||
extern int pm8607_reg_write(struct pm8607_chip *, int, unsigned char);
|
||||
extern int pm8607_bulk_read(struct pm8607_chip *, int, int,
|
||||
unsigned char *);
|
||||
extern int pm8607_bulk_write(struct pm8607_chip *, int, int,
|
||||
unsigned char *);
|
||||
extern int pm8607_set_bits(struct pm8607_chip *, int, unsigned char,
|
||||
unsigned char);
|
||||
#endif /* __LINUX_MFD_88PM8607_H */
|
||||
262
include/linux/mfd/ab4500.h
Normal file
262
include/linux/mfd/ab4500.h
Normal file
|
|
@ -0,0 +1,262 @@
|
|||
/*
|
||||
* Copyright (C) 2009 ST-Ericsson
|
||||
*
|
||||
* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* AB4500 device core funtions, for client access
|
||||
*/
|
||||
#ifndef MFD_AB4500_H
|
||||
#define MFD_AB4500_H
|
||||
|
||||
#include <linux/device.h>
|
||||
|
||||
/*
|
||||
* AB4500 bank addresses
|
||||
*/
|
||||
#define AB4500_SYS_CTRL1_BLOCK 0x1
|
||||
#define AB4500_SYS_CTRL2_BLOCK 0x2
|
||||
#define AB4500_REGU_CTRL1 0x3
|
||||
#define AB4500_REGU_CTRL2 0x4
|
||||
#define AB4500_USB 0x5
|
||||
#define AB4500_TVOUT 0x6
|
||||
#define AB4500_DBI 0x7
|
||||
#define AB4500_ECI_AV_ACC 0x8
|
||||
#define AB4500_RESERVED 0x9
|
||||
#define AB4500_GPADC 0xA
|
||||
#define AB4500_CHARGER 0xB
|
||||
#define AB4500_GAS_GAUGE 0xC
|
||||
#define AB4500_AUDIO 0xD
|
||||
#define AB4500_INTERRUPT 0xE
|
||||
#define AB4500_RTC 0xF
|
||||
#define AB4500_MISC 0x10
|
||||
#define AB4500_DEBUG 0x12
|
||||
#define AB4500_PROD_TEST 0x13
|
||||
#define AB4500_OTP_EMUL 0x15
|
||||
|
||||
/*
|
||||
* System control 1 register offsets.
|
||||
* Bank = 0x01
|
||||
*/
|
||||
#define AB4500_TURNON_STAT_REG 0x0100
|
||||
#define AB4500_RESET_STAT_REG 0x0101
|
||||
#define AB4500_PONKEY1_PRESS_STAT_REG 0x0102
|
||||
|
||||
#define AB4500_FSM_STAT1_REG 0x0140
|
||||
#define AB4500_FSM_STAT2_REG 0x0141
|
||||
#define AB4500_SYSCLK_REQ_STAT_REG 0x0142
|
||||
#define AB4500_USB_STAT1_REG 0x0143
|
||||
#define AB4500_USB_STAT2_REG 0x0144
|
||||
#define AB4500_STATUS_SPARE1_REG 0x0145
|
||||
#define AB4500_STATUS_SPARE2_REG 0x0146
|
||||
|
||||
#define AB4500_CTRL1_REG 0x0180
|
||||
#define AB4500_CTRL2_REG 0x0181
|
||||
|
||||
/*
|
||||
* System control 2 register offsets.
|
||||
* bank = 0x02
|
||||
*/
|
||||
#define AB4500_CTRL3_REG 0x0200
|
||||
#define AB4500_MAIN_WDOG_CTRL_REG 0x0201
|
||||
#define AB4500_MAIN_WDOG_TIMER_REG 0x0202
|
||||
#define AB4500_LOW_BAT_REG 0x0203
|
||||
#define AB4500_BATT_OK_REG 0x0204
|
||||
#define AB4500_SYSCLK_TIMER_REG 0x0205
|
||||
#define AB4500_SMPSCLK_CTRL_REG 0x0206
|
||||
#define AB4500_SMPSCLK_SEL1_REG 0x0207
|
||||
#define AB4500_SMPSCLK_SEL2_REG 0x0208
|
||||
#define AB4500_SMPSCLK_SEL3_REG 0x0209
|
||||
#define AB4500_SYSULPCLK_CONF_REG 0x020A
|
||||
#define AB4500_SYSULPCLK_CTRL1_REG 0x020B
|
||||
#define AB4500_SYSCLK_CTRL_REG 0x020C
|
||||
#define AB4500_SYSCLK_REQ1_VALID_REG 0x020D
|
||||
#define AB4500_SYSCLK_REQ_VALID_REG 0x020E
|
||||
#define AB4500_SYSCTRL_SPARE_REG 0x020F
|
||||
#define AB4500_PAD_CONF_REG 0x0210
|
||||
|
||||
/*
|
||||
* Regu control1 register offsets
|
||||
* Bank = 0x03
|
||||
*/
|
||||
#define AB4500_REGU_SERIAL_CTRL1_REG 0x0300
|
||||
#define AB4500_REGU_SERIAL_CTRL2_REG 0x0301
|
||||
#define AB4500_REGU_SERIAL_CTRL3_REG 0x0302
|
||||
#define AB4500_REGU_REQ_CTRL1_REG 0x0303
|
||||
#define AB4500_REGU_REQ_CTRL2_REG 0x0304
|
||||
#define AB4500_REGU_REQ_CTRL3_REG 0x0305
|
||||
#define AB4500_REGU_REQ_CTRL4_REG 0x0306
|
||||
#define AB4500_REGU_MISC1_REG 0x0380
|
||||
#define AB4500_REGU_OTGSUPPLY_CTRL_REG 0x0381
|
||||
#define AB4500_REGU_VUSB_CTRL_REG 0x0382
|
||||
#define AB4500_REGU_VAUDIO_SUPPLY_REG 0x0383
|
||||
#define AB4500_REGU_CTRL1_SPARE_REG 0x0384
|
||||
|
||||
/*
|
||||
* Regu control2 Vmod register offsets
|
||||
*/
|
||||
#define AB4500_REGU_VMOD_REGU_REG 0x0440
|
||||
#define AB4500_REGU_VMOD_SEL1_REG 0x0441
|
||||
#define AB4500_REGU_VMOD_SEL2_REG 0x0442
|
||||
#define AB4500_REGU_CTRL_DISCH_REG 0x0443
|
||||
#define AB4500_REGU_CTRL_DISCH2_REG 0x0444
|
||||
|
||||
/*
|
||||
* USB/ULPI register offsets
|
||||
* Bank : 0x5
|
||||
*/
|
||||
#define AB4500_USB_LINE_STAT_REG 0x0580
|
||||
#define AB4500_USB_LINE_CTRL1_REG 0x0581
|
||||
#define AB4500_USB_LINE_CTRL2_REG 0x0582
|
||||
#define AB4500_USB_LINE_CTRL3_REG 0x0583
|
||||
#define AB4500_USB_LINE_CTRL4_REG 0x0584
|
||||
#define AB4500_USB_LINE_CTRL5_REG 0x0585
|
||||
#define AB4500_USB_OTG_CTRL_REG 0x0587
|
||||
#define AB4500_USB_OTG_STAT_REG 0x0588
|
||||
#define AB4500_USB_OTG_STAT_REG 0x0588
|
||||
#define AB4500_USB_CTRL_SPARE_REG 0x0589
|
||||
#define AB4500_USB_PHY_CTRL_REG 0x058A
|
||||
|
||||
/*
|
||||
* TVOUT / CTRL register offsets
|
||||
* Bank : 0x06
|
||||
*/
|
||||
#define AB4500_TVOUT_CTRL_REG 0x0680
|
||||
|
||||
/*
|
||||
* DBI register offsets
|
||||
* Bank : 0x07
|
||||
*/
|
||||
#define AB4500_DBI_REG1_REG 0x0700
|
||||
#define AB4500_DBI_REG2_REG 0x0701
|
||||
|
||||
/*
|
||||
* ECI regsiter offsets
|
||||
* Bank : 0x08
|
||||
*/
|
||||
#define AB4500_ECI_CTRL_REG 0x0800
|
||||
#define AB4500_ECI_HOOKLEVEL_REG 0x0801
|
||||
#define AB4500_ECI_DATAOUT_REG 0x0802
|
||||
#define AB4500_ECI_DATAIN_REG 0x0803
|
||||
|
||||
/*
|
||||
* AV Connector register offsets
|
||||
* Bank : 0x08
|
||||
*/
|
||||
#define AB4500_AV_CONN_REG 0x0840
|
||||
|
||||
/*
|
||||
* Accessory detection register offsets
|
||||
* Bank : 0x08
|
||||
*/
|
||||
#define AB4500_ACC_DET_DB1_REG 0x0880
|
||||
#define AB4500_ACC_DET_DB2_REG 0x0881
|
||||
|
||||
/*
|
||||
* GPADC register offsets
|
||||
* Bank : 0x0A
|
||||
*/
|
||||
#define AB4500_GPADC_CTRL1_REG 0x0A00
|
||||
#define AB4500_GPADC_CTRL2_REG 0x0A01
|
||||
#define AB4500_GPADC_CTRL3_REG 0x0A02
|
||||
#define AB4500_GPADC_AUTO_TIMER_REG 0x0A03
|
||||
#define AB4500_GPADC_STAT_REG 0x0A04
|
||||
#define AB4500_GPADC_MANDATAL_REG 0x0A05
|
||||
#define AB4500_GPADC_MANDATAH_REG 0x0A06
|
||||
#define AB4500_GPADC_AUTODATAL_REG 0x0A07
|
||||
#define AB4500_GPADC_AUTODATAH_REG 0x0A08
|
||||
#define AB4500_GPADC_MUX_CTRL_REG 0x0A09
|
||||
|
||||
/*
|
||||
* Charger / status register offfsets
|
||||
* Bank : 0x0B
|
||||
*/
|
||||
#define AB4500_CH_STATUS1_REG 0x0B00
|
||||
#define AB4500_CH_STATUS2_REG 0x0B01
|
||||
#define AB4500_CH_USBCH_STAT1_REG 0x0B02
|
||||
#define AB4500_CH_USBCH_STAT2_REG 0x0B03
|
||||
#define AB4500_CH_FSM_STAT_REG 0x0B04
|
||||
#define AB4500_CH_STAT_REG 0x0B05
|
||||
|
||||
/*
|
||||
* Charger / control register offfsets
|
||||
* Bank : 0x0B
|
||||
*/
|
||||
#define AB4500_CH_VOLT_LVL_REG 0x0B40
|
||||
|
||||
/*
|
||||
* Charger / main control register offfsets
|
||||
* Bank : 0x0B
|
||||
*/
|
||||
#define AB4500_MCH_CTRL1 0x0B80
|
||||
#define AB4500_MCH_CTRL2 0x0B81
|
||||
#define AB4500_MCH_IPT_CURLVL_REG 0x0B82
|
||||
#define AB4500_CH_WD_REG 0x0B83
|
||||
|
||||
/*
|
||||
* Charger / USB control register offsets
|
||||
* Bank : 0x0B
|
||||
*/
|
||||
#define AB4500_USBCH_CTRL1_REG 0x0BC0
|
||||
#define AB4500_USBCH_CTRL2_REG 0x0BC1
|
||||
#define AB4500_USBCH_IPT_CRNTLVL_REG 0x0BC2
|
||||
|
||||
/*
|
||||
* RTC bank register offsets
|
||||
* Bank : 0xF
|
||||
*/
|
||||
#define AB4500_RTC_SOFF_STAT_REG 0x0F00
|
||||
#define AB4500_RTC_CC_CONF_REG 0x0F01
|
||||
#define AB4500_RTC_READ_REQ_REG 0x0F02
|
||||
#define AB4500_RTC_WATCH_TSECMID_REG 0x0F03
|
||||
#define AB4500_RTC_WATCH_TSECHI_REG 0x0F04
|
||||
#define AB4500_RTC_WATCH_TMIN_LOW_REG 0x0F05
|
||||
#define AB4500_RTC_WATCH_TMIN_MID_REG 0x0F06
|
||||
#define AB4500_RTC_WATCH_TMIN_HI_REG 0x0F07
|
||||
#define AB4500_RTC_ALRM_MIN_LOW_REG 0x0F08
|
||||
#define AB4500_RTC_ALRM_MIN_MID_REG 0x0F09
|
||||
#define AB4500_RTC_ALRM_MIN_HI_REG 0x0F0A
|
||||
#define AB4500_RTC_STAT_REG 0x0F0B
|
||||
#define AB4500_RTC_BKUP_CHG_REG 0x0F0C
|
||||
#define AB4500_RTC_FORCE_BKUP_REG 0x0F0D
|
||||
#define AB4500_RTC_CALIB_REG 0x0F0E
|
||||
#define AB4500_RTC_SWITCH_STAT_REG 0x0F0F
|
||||
|
||||
/*
|
||||
* PWM Out generators
|
||||
* Bank: 0x10
|
||||
*/
|
||||
#define AB4500_PWM_OUT_CTRL1_REG 0x1060
|
||||
#define AB4500_PWM_OUT_CTRL2_REG 0x1061
|
||||
#define AB4500_PWM_OUT_CTRL3_REG 0x1062
|
||||
#define AB4500_PWM_OUT_CTRL4_REG 0x1063
|
||||
#define AB4500_PWM_OUT_CTRL5_REG 0x1064
|
||||
#define AB4500_PWM_OUT_CTRL6_REG 0x1065
|
||||
#define AB4500_PWM_OUT_CTRL7_REG 0x1066
|
||||
|
||||
#define AB4500_I2C_PAD_CTRL_REG 0x1067
|
||||
#define AB4500_REV_REG 0x1080
|
||||
|
||||
/**
|
||||
* struct ab4500
|
||||
* @spi: spi device structure
|
||||
* @tx_buf: transmit buffer
|
||||
* @rx_buf: receive buffer
|
||||
* @lock: sync primitive
|
||||
*/
|
||||
struct ab4500 {
|
||||
struct spi_device *spi;
|
||||
unsigned long tx_buf[4];
|
||||
unsigned long rx_buf[4];
|
||||
struct mutex lock;
|
||||
};
|
||||
|
||||
int ab4500_write(struct ab4500 *ab4500, unsigned char block,
|
||||
unsigned long addr, unsigned char data);
|
||||
int ab4500_read(struct ab4500 *ab4500, unsigned char block,
|
||||
unsigned long addr);
|
||||
|
||||
#endif /* MFD_AB4500_H */
|
||||
299
include/linux/mfd/adp5520.h
Normal file
299
include/linux/mfd/adp5520.h
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
/*
|
||||
* Definitions and platform data for Analog Devices
|
||||
* ADP5520/ADP5501 MFD PMICs (Backlight, LED, GPIO and Keys)
|
||||
*
|
||||
* Copyright 2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __LINUX_MFD_ADP5520_H
|
||||
#define __LINUX_MFD_ADP5520_H
|
||||
|
||||
#define ID_ADP5520 5520
|
||||
#define ID_ADP5501 5501
|
||||
|
||||
/*
|
||||
* ADP5520/ADP5501 Register Map
|
||||
*/
|
||||
|
||||
#define ADP5520_MODE_STATUS 0x00
|
||||
#define ADP5520_INTERRUPT_ENABLE 0x01
|
||||
#define ADP5520_BL_CONTROL 0x02
|
||||
#define ADP5520_BL_TIME 0x03
|
||||
#define ADP5520_BL_FADE 0x04
|
||||
#define ADP5520_DAYLIGHT_MAX 0x05
|
||||
#define ADP5520_DAYLIGHT_DIM 0x06
|
||||
#define ADP5520_OFFICE_MAX 0x07
|
||||
#define ADP5520_OFFICE_DIM 0x08
|
||||
#define ADP5520_DARK_MAX 0x09
|
||||
#define ADP5520_DARK_DIM 0x0A
|
||||
#define ADP5520_BL_VALUE 0x0B
|
||||
#define ADP5520_ALS_CMPR_CFG 0x0C
|
||||
#define ADP5520_L2_TRIP 0x0D
|
||||
#define ADP5520_L2_HYS 0x0E
|
||||
#define ADP5520_L3_TRIP 0x0F
|
||||
#define ADP5520_L3_HYS 0x10
|
||||
#define ADP5520_LED_CONTROL 0x11
|
||||
#define ADP5520_LED_TIME 0x12
|
||||
#define ADP5520_LED_FADE 0x13
|
||||
#define ADP5520_LED1_CURRENT 0x14
|
||||
#define ADP5520_LED2_CURRENT 0x15
|
||||
#define ADP5520_LED3_CURRENT 0x16
|
||||
|
||||
/*
|
||||
* ADP5520 Register Map
|
||||
*/
|
||||
|
||||
#define ADP5520_GPIO_CFG_1 0x17
|
||||
#define ADP5520_GPIO_CFG_2 0x18
|
||||
#define ADP5520_GPIO_IN 0x19
|
||||
#define ADP5520_GPIO_OUT 0x1A
|
||||
#define ADP5520_GPIO_INT_EN 0x1B
|
||||
#define ADP5520_GPIO_INT_STAT 0x1C
|
||||
#define ADP5520_GPIO_INT_LVL 0x1D
|
||||
#define ADP5520_GPIO_DEBOUNCE 0x1E
|
||||
#define ADP5520_GPIO_PULLUP 0x1F
|
||||
#define ADP5520_KP_INT_STAT_1 0x20
|
||||
#define ADP5520_KP_INT_STAT_2 0x21
|
||||
#define ADP5520_KR_INT_STAT_1 0x22
|
||||
#define ADP5520_KR_INT_STAT_2 0x23
|
||||
#define ADP5520_KEY_STAT_1 0x24
|
||||
#define ADP5520_KEY_STAT_2 0x25
|
||||
|
||||
/*
|
||||
* MODE_STATUS bits
|
||||
*/
|
||||
|
||||
#define ADP5520_nSTNBY (1 << 7)
|
||||
#define ADP5520_BL_EN (1 << 6)
|
||||
#define ADP5520_DIM_EN (1 << 5)
|
||||
#define ADP5520_OVP_INT (1 << 4)
|
||||
#define ADP5520_CMPR_INT (1 << 3)
|
||||
#define ADP5520_GPI_INT (1 << 2)
|
||||
#define ADP5520_KR_INT (1 << 1)
|
||||
#define ADP5520_KP_INT (1 << 0)
|
||||
|
||||
/*
|
||||
* INTERRUPT_ENABLE bits
|
||||
*/
|
||||
|
||||
#define ADP5520_AUTO_LD_EN (1 << 4)
|
||||
#define ADP5520_CMPR_IEN (1 << 3)
|
||||
#define ADP5520_OVP_IEN (1 << 2)
|
||||
#define ADP5520_KR_IEN (1 << 1)
|
||||
#define ADP5520_KP_IEN (1 << 0)
|
||||
|
||||
/*
|
||||
* BL_CONTROL bits
|
||||
*/
|
||||
|
||||
#define ADP5520_BL_LVL ((x) << 5)
|
||||
#define ADP5520_BL_LAW ((x) << 4)
|
||||
#define ADP5520_BL_AUTO_ADJ (1 << 3)
|
||||
#define ADP5520_OVP_EN (1 << 2)
|
||||
#define ADP5520_FOVR (1 << 1)
|
||||
#define ADP5520_KP_BL_EN (1 << 0)
|
||||
|
||||
/*
|
||||
* ALS_CMPR_CFG bits
|
||||
*/
|
||||
|
||||
#define ADP5520_L3_OUT (1 << 3)
|
||||
#define ADP5520_L2_OUT (1 << 2)
|
||||
#define ADP5520_L3_EN (1 << 1)
|
||||
|
||||
#define ADP5020_MAX_BRIGHTNESS 0x7F
|
||||
|
||||
#define FADE_VAL(in, out) ((0xF & (in)) | ((0xF & (out)) << 4))
|
||||
#define BL_CTRL_VAL(law, auto) (((1 & (auto)) << 3) | ((0x3 & (law)) << 4))
|
||||
#define ALS_CMPR_CFG_VAL(filt, l3_en) (((0x7 & filt) << 5) | l3_en)
|
||||
|
||||
/*
|
||||
* LEDs subdevice bits and masks
|
||||
*/
|
||||
|
||||
#define ADP5520_01_MAXLEDS 3
|
||||
|
||||
#define ADP5520_FLAG_LED_MASK 0x3
|
||||
#define ADP5520_FLAG_OFFT_SHIFT 8
|
||||
#define ADP5520_FLAG_OFFT_MASK 0x3
|
||||
|
||||
#define ADP5520_R3_MODE (1 << 5)
|
||||
#define ADP5520_C3_MODE (1 << 4)
|
||||
#define ADP5520_LED_LAW (1 << 3)
|
||||
#define ADP5520_LED3_EN (1 << 2)
|
||||
#define ADP5520_LED2_EN (1 << 1)
|
||||
#define ADP5520_LED1_EN (1 << 0)
|
||||
|
||||
/*
|
||||
* GPIO subdevice bits and masks
|
||||
*/
|
||||
|
||||
#define ADP5520_MAXGPIOS 8
|
||||
|
||||
#define ADP5520_GPIO_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
|
||||
#define ADP5520_GPIO_C2 (1 << 6)
|
||||
#define ADP5520_GPIO_C1 (1 << 5)
|
||||
#define ADP5520_GPIO_C0 (1 << 4)
|
||||
#define ADP5520_GPIO_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
|
||||
#define ADP5520_GPIO_R2 (1 << 2)
|
||||
#define ADP5520_GPIO_R1 (1 << 1)
|
||||
#define ADP5520_GPIO_R0 (1 << 0)
|
||||
|
||||
struct adp5520_gpio_platform_data {
|
||||
unsigned gpio_start;
|
||||
u8 gpio_en_mask;
|
||||
u8 gpio_pullup_mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* Keypad subdevice bits and masks
|
||||
*/
|
||||
|
||||
#define ADP5520_MAXKEYS 16
|
||||
|
||||
#define ADP5520_COL_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
|
||||
#define ADP5520_COL_C2 (1 << 6)
|
||||
#define ADP5520_COL_C1 (1 << 5)
|
||||
#define ADP5520_COL_C0 (1 << 4)
|
||||
#define ADP5520_ROW_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
|
||||
#define ADP5520_ROW_R2 (1 << 2)
|
||||
#define ADP5520_ROW_R1 (1 << 1)
|
||||
#define ADP5520_ROW_R0 (1 << 0)
|
||||
|
||||
#define ADP5520_KEY(row, col) (col + row * 4)
|
||||
#define ADP5520_KEYMAPSIZE ADP5520_MAXKEYS
|
||||
|
||||
struct adp5520_keys_platform_data {
|
||||
int rows_en_mask; /* Number of rows */
|
||||
int cols_en_mask; /* Number of columns */
|
||||
const unsigned short *keymap; /* Pointer to keymap */
|
||||
unsigned short keymapsize; /* Keymap size */
|
||||
unsigned repeat:1; /* Enable key repeat */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* LEDs subdevice platform data
|
||||
*/
|
||||
|
||||
#define FLAG_ID_ADP5520_LED1_ADP5501_LED0 1 /* ADP5520 PIN ILED */
|
||||
#define FLAG_ID_ADP5520_LED2_ADP5501_LED1 2 /* ADP5520 PIN C3 */
|
||||
#define FLAG_ID_ADP5520_LED3_ADP5501_LED2 3 /* ADP5520 PIN R3 */
|
||||
|
||||
#define ADP5520_LED_DIS_BLINK (0 << ADP5520_FLAG_OFFT_SHIFT)
|
||||
#define ADP5520_LED_OFFT_600ms (1 << ADP5520_FLAG_OFFT_SHIFT)
|
||||
#define ADP5520_LED_OFFT_800ms (2 << ADP5520_FLAG_OFFT_SHIFT)
|
||||
#define ADP5520_LED_OFFT_1200ms (3 << ADP5520_FLAG_OFFT_SHIFT)
|
||||
|
||||
#define ADP5520_LED_ONT_200ms 0
|
||||
#define ADP5520_LED_ONT_600ms 1
|
||||
#define ADP5520_LED_ONT_800ms 2
|
||||
#define ADP5520_LED_ONT_1200ms 3
|
||||
|
||||
struct adp5520_leds_platform_data {
|
||||
int num_leds;
|
||||
struct led_info *leds;
|
||||
u8 fade_in; /* Backlight Fade-In Timer */
|
||||
u8 fade_out; /* Backlight Fade-Out Timer */
|
||||
u8 led_on_time;
|
||||
};
|
||||
|
||||
/*
|
||||
* Backlight subdevice platform data
|
||||
*/
|
||||
|
||||
#define ADP5520_FADE_T_DIS 0 /* Fade Timer Disabled */
|
||||
#define ADP5520_FADE_T_300ms 1 /* 0.3 Sec */
|
||||
#define ADP5520_FADE_T_600ms 2
|
||||
#define ADP5520_FADE_T_900ms 3
|
||||
#define ADP5520_FADE_T_1200ms 4
|
||||
#define ADP5520_FADE_T_1500ms 5
|
||||
#define ADP5520_FADE_T_1800ms 6
|
||||
#define ADP5520_FADE_T_2100ms 7
|
||||
#define ADP5520_FADE_T_2400ms 8
|
||||
#define ADP5520_FADE_T_2700ms 9
|
||||
#define ADP5520_FADE_T_3000ms 10
|
||||
#define ADP5520_FADE_T_3500ms 11
|
||||
#define ADP5520_FADE_T_4000ms 12
|
||||
#define ADP5520_FADE_T_4500ms 13
|
||||
#define ADP5520_FADE_T_5000ms 14
|
||||
#define ADP5520_FADE_T_5500ms 15 /* 5.5 Sec */
|
||||
|
||||
#define ADP5520_BL_LAW_LINEAR 0
|
||||
#define ADP5520_BL_LAW_SQUARE 1
|
||||
#define ADP5520_BL_LAW_CUBIC1 2
|
||||
#define ADP5520_BL_LAW_CUBIC2 3
|
||||
|
||||
#define ADP5520_BL_AMBL_FILT_80ms 0 /* Light sensor filter time */
|
||||
#define ADP5520_BL_AMBL_FILT_160ms 1
|
||||
#define ADP5520_BL_AMBL_FILT_320ms 2
|
||||
#define ADP5520_BL_AMBL_FILT_640ms 3
|
||||
#define ADP5520_BL_AMBL_FILT_1280ms 4
|
||||
#define ADP5520_BL_AMBL_FILT_2560ms 5
|
||||
#define ADP5520_BL_AMBL_FILT_5120ms 6
|
||||
#define ADP5520_BL_AMBL_FILT_10240ms 7 /* 10.24 sec */
|
||||
|
||||
/*
|
||||
* Blacklight current 0..30mA
|
||||
*/
|
||||
#define ADP5520_BL_CUR_mA(I) ((I * 127) / 30)
|
||||
|
||||
/*
|
||||
* L2 comparator current 0..1000uA
|
||||
*/
|
||||
#define ADP5520_L2_COMP_CURR_uA(I) ((I * 255) / 1000)
|
||||
|
||||
/*
|
||||
* L3 comparator current 0..127uA
|
||||
*/
|
||||
#define ADP5520_L3_COMP_CURR_uA(I) ((I * 255) / 127)
|
||||
|
||||
struct adp5520_backlight_platform_data {
|
||||
u8 fade_in; /* Backlight Fade-In Timer */
|
||||
u8 fade_out; /* Backlight Fade-Out Timer */
|
||||
u8 fade_led_law; /* fade-on/fade-off transfer characteristic */
|
||||
|
||||
u8 en_ambl_sens; /* 1 = enable ambient light sensor */
|
||||
u8 abml_filt; /* Light sensor filter time */
|
||||
u8 l1_daylight_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
|
||||
u8 l1_daylight_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
|
||||
u8 l2_office_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
|
||||
u8 l2_office_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
|
||||
u8 l3_dark_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
|
||||
u8 l3_dark_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
|
||||
u8 l2_trip; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
|
||||
u8 l2_hyst; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
|
||||
u8 l3_trip; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
|
||||
u8 l3_hyst; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
|
||||
};
|
||||
|
||||
/*
|
||||
* MFD chip platform data
|
||||
*/
|
||||
|
||||
struct adp5520_platform_data {
|
||||
struct adp5520_keys_platform_data *keys;
|
||||
struct adp5520_gpio_platform_data *gpio;
|
||||
struct adp5520_leds_platform_data *leds;
|
||||
struct adp5520_backlight_platform_data *backlight;
|
||||
};
|
||||
|
||||
/*
|
||||
* MFD chip functions
|
||||
*/
|
||||
|
||||
extern int adp5520_read(struct device *dev, int reg, uint8_t *val);
|
||||
extern int adp5520_write(struct device *dev, int reg, u8 val);
|
||||
extern int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
|
||||
extern int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask);
|
||||
|
||||
extern int adp5520_register_notifier(struct device *dev,
|
||||
struct notifier_block *nb, unsigned int events);
|
||||
|
||||
extern int adp5520_unregister_notifier(struct device *dev,
|
||||
struct notifier_block *nb, unsigned int events);
|
||||
|
||||
#endif /* __LINUX_MFD_ADP5520_H */
|
||||
|
|
@ -231,9 +231,6 @@ void pcap_set_ts_bits(struct pcap_chip *, u32);
|
|||
#define PCAP_LED_4MA 1
|
||||
#define PCAP_LED_5MA 2
|
||||
#define PCAP_LED_9MA 3
|
||||
#define PCAP_LED_GPIO_VAL_MASK 0x00ffffff
|
||||
#define PCAP_LED_GPIO_EN 0x01000000
|
||||
#define PCAP_LED_GPIO_INVERT 0x02000000
|
||||
#define PCAP_LED_T_MASK 0xf
|
||||
#define PCAP_LED_C_MASK 0x3
|
||||
#define PCAP_BL_MASK 0x1f
|
||||
|
|
|
|||
|
|
@ -24,52 +24,23 @@
|
|||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mfd/mc13783.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
struct mc13783_irq {
|
||||
void (*handler)(int, void *);
|
||||
void *data;
|
||||
};
|
||||
|
||||
#define MC13783_NUM_IRQ 2
|
||||
#define MC13783_IRQ_TS 0
|
||||
#define MC13783_IRQ_REGULATOR 1
|
||||
|
||||
#define MC13783_ADC_MODE_TS 1
|
||||
#define MC13783_ADC_MODE_SINGLE_CHAN 2
|
||||
#define MC13783_ADC_MODE_MULT_CHAN 3
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
struct mc13783 {
|
||||
int revision;
|
||||
struct device *dev;
|
||||
struct spi_device *spi_device;
|
||||
|
||||
int (*read_dev)(void *data, char reg, int count, u32 *dst);
|
||||
int (*write_dev)(void *data, char reg, int count, const u32 *src);
|
||||
|
||||
struct mutex io_lock;
|
||||
void *io_data;
|
||||
struct spi_device *spidev;
|
||||
struct mutex lock;
|
||||
int irq;
|
||||
unsigned int flags;
|
||||
int flags;
|
||||
|
||||
struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
|
||||
struct work_struct work;
|
||||
struct completion adc_done;
|
||||
unsigned int ts_active;
|
||||
struct mutex adc_conv_lock;
|
||||
irq_handler_t irqhandler[MC13783_NUM_IRQ];
|
||||
void *irqdata[MC13783_NUM_IRQ];
|
||||
|
||||
/* XXX these should go as platformdata to the regulator subdevice */
|
||||
struct mc13783_regulator_init_data *regulators;
|
||||
int num_regulators;
|
||||
};
|
||||
|
||||
int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
|
||||
int mc13783_reg_write(struct mc13783 *, int, u32);
|
||||
int mc13783_set_bits(struct mc13783 *, int, u32, u32);
|
||||
int mc13783_free_irq(struct mc13783 *mc13783, int irq);
|
||||
int mc13783_register_irq(struct mc13783 *mc13783, int irq,
|
||||
void (*handler) (int, void *), void *data);
|
||||
|
||||
#define MC13783_REG_INTERRUPT_STATUS_0 0
|
||||
#define MC13783_REG_INTERRUPT_MASK_0 1
|
||||
#define MC13783_REG_INTERRUPT_SENSE_0 2
|
||||
|
|
@ -136,55 +107,6 @@ int mc13783_register_irq(struct mc13783 *mc13783, int irq,
|
|||
#define MC13783_REG_TEST_3 63
|
||||
#define MC13783_REG_NB 64
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Status
|
||||
*/
|
||||
#define MC13783_INT_STAT_ADCDONEI (1 << 0)
|
||||
#define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
|
||||
#define MC13783_INT_STAT_TSI (1 << 2)
|
||||
#define MC13783_INT_STAT_WHIGHI (1 << 3)
|
||||
#define MC13783_INT_STAT_WLOWI (1 << 4)
|
||||
#define MC13783_INT_STAT_CHGDETI (1 << 6)
|
||||
#define MC13783_INT_STAT_CHGOVI (1 << 7)
|
||||
#define MC13783_INT_STAT_CHGREVI (1 << 8)
|
||||
#define MC13783_INT_STAT_CHGSHORTI (1 << 9)
|
||||
#define MC13783_INT_STAT_CCCVI (1 << 10)
|
||||
#define MC13783_INT_STAT_CHGCURRI (1 << 11)
|
||||
#define MC13783_INT_STAT_BPONI (1 << 12)
|
||||
#define MC13783_INT_STAT_LOBATLI (1 << 13)
|
||||
#define MC13783_INT_STAT_LOBATHI (1 << 14)
|
||||
#define MC13783_INT_STAT_UDPI (1 << 15)
|
||||
#define MC13783_INT_STAT_USBI (1 << 16)
|
||||
#define MC13783_INT_STAT_IDI (1 << 19)
|
||||
#define MC13783_INT_STAT_Unused (1 << 20)
|
||||
#define MC13783_INT_STAT_SE1I (1 << 21)
|
||||
#define MC13783_INT_STAT_CKDETI (1 << 22)
|
||||
#define MC13783_INT_STAT_UDMI (1 << 23)
|
||||
|
||||
/*
|
||||
* Interrupt Mask
|
||||
*/
|
||||
#define MC13783_INT_MASK_ADCDONEM (1 << 0)
|
||||
#define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
|
||||
#define MC13783_INT_MASK_TSM (1 << 2)
|
||||
#define MC13783_INT_MASK_WHIGHM (1 << 3)
|
||||
#define MC13783_INT_MASK_WLOWM (1 << 4)
|
||||
#define MC13783_INT_MASK_CHGDETM (1 << 6)
|
||||
#define MC13783_INT_MASK_CHGOVM (1 << 7)
|
||||
#define MC13783_INT_MASK_CHGREVM (1 << 8)
|
||||
#define MC13783_INT_MASK_CHGSHORTM (1 << 9)
|
||||
#define MC13783_INT_MASK_CCCVM (1 << 10)
|
||||
#define MC13783_INT_MASK_CHGCURRM (1 << 11)
|
||||
#define MC13783_INT_MASK_BPONM (1 << 12)
|
||||
#define MC13783_INT_MASK_LOBATLM (1 << 13)
|
||||
#define MC13783_INT_MASK_LOBATHM (1 << 14)
|
||||
#define MC13783_INT_MASK_UDPM (1 << 15)
|
||||
#define MC13783_INT_MASK_USBM (1 << 16)
|
||||
#define MC13783_INT_MASK_IDM (1 << 19)
|
||||
#define MC13783_INT_MASK_SE1M (1 << 21)
|
||||
#define MC13783_INT_MASK_CKDETM (1 << 22)
|
||||
|
||||
/*
|
||||
* Reg Regulator Mode 0
|
||||
*/
|
||||
|
|
@ -284,113 +206,15 @@ int mc13783_register_irq(struct mc13783 *mc13783, int irq,
|
|||
#define MC13783_SWCTRL_SW3_STBY (1 << 21)
|
||||
#define MC13783_SWCTRL_SW3_MODE (1 << 22)
|
||||
|
||||
/*
|
||||
* ADC/Touch
|
||||
*/
|
||||
#define MC13783_ADC0_LICELLCON (1 << 0)
|
||||
#define MC13783_ADC0_CHRGICON (1 << 1)
|
||||
#define MC13783_ADC0_BATICON (1 << 2)
|
||||
#define MC13783_ADC0_RTHEN (1 << 3)
|
||||
#define MC13783_ADC0_DTHEN (1 << 4)
|
||||
#define MC13783_ADC0_UIDEN (1 << 5)
|
||||
#define MC13783_ADC0_ADOUTEN (1 << 6)
|
||||
#define MC13783_ADC0_ADOUTPER (1 << 7)
|
||||
#define MC13783_ADC0_ADREFEN (1 << 10)
|
||||
#define MC13783_ADC0_ADREFMODE (1 << 11)
|
||||
#define MC13783_ADC0_TSMOD0 (1 << 12)
|
||||
#define MC13783_ADC0_TSMOD1 (1 << 13)
|
||||
#define MC13783_ADC0_TSMOD2 (1 << 14)
|
||||
#define MC13783_ADC0_CHRGRAWDIV (1 << 15)
|
||||
#define MC13783_ADC0_ADINC1 (1 << 16)
|
||||
#define MC13783_ADC0_ADINC2 (1 << 17)
|
||||
#define MC13783_ADC0_WCOMP (1 << 18)
|
||||
#define MC13783_ADC0_ADCBIS0 (1 << 23)
|
||||
static inline int mc13783_set_bits(struct mc13783 *mc13783, unsigned int offset,
|
||||
u32 mask, u32 val)
|
||||
{
|
||||
int ret;
|
||||
mc13783_lock(mc13783);
|
||||
ret = mc13783_reg_rmw(mc13783, offset, mask, val);
|
||||
mc13783_unlock(mc13783);
|
||||
|
||||
#define MC13783_ADC1_ADEN (1 << 0)
|
||||
#define MC13783_ADC1_RAND (1 << 1)
|
||||
#define MC13783_ADC1_ADSEL (1 << 3)
|
||||
#define MC13783_ADC1_TRIGMASK (1 << 4)
|
||||
#define MC13783_ADC1_ADA10 (1 << 5)
|
||||
#define MC13783_ADC1_ADA11 (1 << 6)
|
||||
#define MC13783_ADC1_ADA12 (1 << 7)
|
||||
#define MC13783_ADC1_ADA20 (1 << 8)
|
||||
#define MC13783_ADC1_ADA21 (1 << 9)
|
||||
#define MC13783_ADC1_ADA22 (1 << 10)
|
||||
#define MC13783_ADC1_ATO0 (1 << 11)
|
||||
#define MC13783_ADC1_ATO1 (1 << 12)
|
||||
#define MC13783_ADC1_ATO2 (1 << 13)
|
||||
#define MC13783_ADC1_ATO3 (1 << 14)
|
||||
#define MC13783_ADC1_ATO4 (1 << 15)
|
||||
#define MC13783_ADC1_ATO5 (1 << 16)
|
||||
#define MC13783_ADC1_ATO6 (1 << 17)
|
||||
#define MC13783_ADC1_ATO7 (1 << 18)
|
||||
#define MC13783_ADC1_ATOX (1 << 19)
|
||||
#define MC13783_ADC1_ASC (1 << 20)
|
||||
#define MC13783_ADC1_ADTRIGIGN (1 << 21)
|
||||
#define MC13783_ADC1_ADONESHOT (1 << 22)
|
||||
#define MC13783_ADC1_ADCBIS1 (1 << 23)
|
||||
|
||||
#define MC13783_ADC1_CHAN0_SHIFT 5
|
||||
#define MC13783_ADC1_CHAN1_SHIFT 8
|
||||
|
||||
#define MC13783_ADC2_ADD10 (1 << 2)
|
||||
#define MC13783_ADC2_ADD11 (1 << 3)
|
||||
#define MC13783_ADC2_ADD12 (1 << 4)
|
||||
#define MC13783_ADC2_ADD13 (1 << 5)
|
||||
#define MC13783_ADC2_ADD14 (1 << 6)
|
||||
#define MC13783_ADC2_ADD15 (1 << 7)
|
||||
#define MC13783_ADC2_ADD16 (1 << 8)
|
||||
#define MC13783_ADC2_ADD17 (1 << 9)
|
||||
#define MC13783_ADC2_ADD18 (1 << 10)
|
||||
#define MC13783_ADC2_ADD19 (1 << 11)
|
||||
#define MC13783_ADC2_ADD20 (1 << 14)
|
||||
#define MC13783_ADC2_ADD21 (1 << 15)
|
||||
#define MC13783_ADC2_ADD22 (1 << 16)
|
||||
#define MC13783_ADC2_ADD23 (1 << 17)
|
||||
#define MC13783_ADC2_ADD24 (1 << 18)
|
||||
#define MC13783_ADC2_ADD25 (1 << 19)
|
||||
#define MC13783_ADC2_ADD26 (1 << 20)
|
||||
#define MC13783_ADC2_ADD27 (1 << 21)
|
||||
#define MC13783_ADC2_ADD28 (1 << 22)
|
||||
#define MC13783_ADC2_ADD29 (1 << 23)
|
||||
|
||||
#define MC13783_ADC3_WHIGH0 (1 << 0)
|
||||
#define MC13783_ADC3_WHIGH1 (1 << 1)
|
||||
#define MC13783_ADC3_WHIGH2 (1 << 2)
|
||||
#define MC13783_ADC3_WHIGH3 (1 << 3)
|
||||
#define MC13783_ADC3_WHIGH4 (1 << 4)
|
||||
#define MC13783_ADC3_WHIGH5 (1 << 5)
|
||||
#define MC13783_ADC3_ICID0 (1 << 6)
|
||||
#define MC13783_ADC3_ICID1 (1 << 7)
|
||||
#define MC13783_ADC3_ICID2 (1 << 8)
|
||||
#define MC13783_ADC3_WLOW0 (1 << 9)
|
||||
#define MC13783_ADC3_WLOW1 (1 << 10)
|
||||
#define MC13783_ADC3_WLOW2 (1 << 11)
|
||||
#define MC13783_ADC3_WLOW3 (1 << 12)
|
||||
#define MC13783_ADC3_WLOW4 (1 << 13)
|
||||
#define MC13783_ADC3_WLOW5 (1 << 14)
|
||||
#define MC13783_ADC3_ADCBIS2 (1 << 23)
|
||||
|
||||
#define MC13783_ADC4_ADDBIS10 (1 << 2)
|
||||
#define MC13783_ADC4_ADDBIS11 (1 << 3)
|
||||
#define MC13783_ADC4_ADDBIS12 (1 << 4)
|
||||
#define MC13783_ADC4_ADDBIS13 (1 << 5)
|
||||
#define MC13783_ADC4_ADDBIS14 (1 << 6)
|
||||
#define MC13783_ADC4_ADDBIS15 (1 << 7)
|
||||
#define MC13783_ADC4_ADDBIS16 (1 << 8)
|
||||
#define MC13783_ADC4_ADDBIS17 (1 << 9)
|
||||
#define MC13783_ADC4_ADDBIS18 (1 << 10)
|
||||
#define MC13783_ADC4_ADDBIS19 (1 << 11)
|
||||
#define MC13783_ADC4_ADDBIS20 (1 << 14)
|
||||
#define MC13783_ADC4_ADDBIS21 (1 << 15)
|
||||
#define MC13783_ADC4_ADDBIS22 (1 << 16)
|
||||
#define MC13783_ADC4_ADDBIS23 (1 << 17)
|
||||
#define MC13783_ADC4_ADDBIS24 (1 << 18)
|
||||
#define MC13783_ADC4_ADDBIS25 (1 << 19)
|
||||
#define MC13783_ADC4_ADDBIS26 (1 << 20)
|
||||
#define MC13783_ADC4_ADDBIS27 (1 << 21)
|
||||
#define MC13783_ADC4_ADDBIS28 (1 << 22)
|
||||
#define MC13783_ADC4_ADDBIS29 (1 << 23)
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* __LINUX_MFD_MC13783_PRIV_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,28 +1,50 @@
|
|||
/*
|
||||
* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
||||
* Copyright 2009 Pengutronix
|
||||
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
|
||||
*
|
||||
* Initial development of this code was funded by
|
||||
* Phytec Messtechnik GmbH, http://www.phytec.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#ifndef __LINUX_MFD_MC13783_H
|
||||
#define __LINUX_MFD_MC13783_H
|
||||
|
||||
#ifndef __INCLUDE_LINUX_MFD_MC13783_H
|
||||
#define __INCLUDE_LINUX_MFD_MC13783_H
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
struct mc13783;
|
||||
|
||||
void mc13783_lock(struct mc13783 *mc13783);
|
||||
void mc13783_unlock(struct mc13783 *mc13783);
|
||||
|
||||
int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val);
|
||||
int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val);
|
||||
int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
|
||||
u32 mask, u32 val);
|
||||
|
||||
int mc13783_irq_request(struct mc13783 *mc13783, int irq,
|
||||
irq_handler_t handler, const char *name, void *dev);
|
||||
int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
|
||||
irq_handler_t handler, const char *name, void *dev);
|
||||
int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev);
|
||||
int mc13783_ackirq(struct mc13783 *mc13783, int irq);
|
||||
|
||||
int mc13783_mask(struct mc13783 *mc13783, int irq);
|
||||
int mc13783_unmask(struct mc13783 *mc13783, int irq);
|
||||
|
||||
#define MC13783_ADC0 43
|
||||
#define MC13783_ADC0_ADREFEN (1 << 10)
|
||||
#define MC13783_ADC0_ADREFMODE (1 << 11)
|
||||
#define MC13783_ADC0_TSMOD0 (1 << 12)
|
||||
#define MC13783_ADC0_TSMOD1 (1 << 13)
|
||||
#define MC13783_ADC0_TSMOD2 (1 << 14)
|
||||
#define MC13783_ADC0_ADINC1 (1 << 16)
|
||||
#define MC13783_ADC0_ADINC2 (1 << 17)
|
||||
|
||||
#define MC13783_ADC0_TSMOD_MASK (MC13783_ADC0_TSMOD0 | \
|
||||
MC13783_ADC0_TSMOD1 | \
|
||||
MC13783_ADC0_TSMOD2)
|
||||
|
||||
/* to be cleaned up */
|
||||
struct regulator_init_data;
|
||||
|
||||
struct mc13783_regulator_init_data {
|
||||
|
|
@ -30,23 +52,30 @@ struct mc13783_regulator_init_data {
|
|||
struct regulator_init_data *init_data;
|
||||
};
|
||||
|
||||
struct mc13783_platform_data {
|
||||
struct mc13783_regulator_init_data *regulators;
|
||||
struct mc13783_regulator_platform_data {
|
||||
int num_regulators;
|
||||
unsigned int flags;
|
||||
struct mc13783_regulator_init_data *regulators;
|
||||
};
|
||||
|
||||
/* mc13783_platform_data flags */
|
||||
struct mc13783_platform_data {
|
||||
int num_regulators;
|
||||
struct mc13783_regulator_init_data *regulators;
|
||||
|
||||
#define MC13783_USE_TOUCHSCREEN (1 << 0)
|
||||
#define MC13783_USE_CODEC (1 << 1)
|
||||
#define MC13783_USE_ADC (1 << 2)
|
||||
#define MC13783_USE_RTC (1 << 3)
|
||||
#define MC13783_USE_REGULATOR (1 << 4)
|
||||
unsigned int flags;
|
||||
};
|
||||
|
||||
#define MC13783_ADC_MODE_TS 1
|
||||
#define MC13783_ADC_MODE_SINGLE_CHAN 2
|
||||
#define MC13783_ADC_MODE_MULT_CHAN 3
|
||||
|
||||
int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
|
||||
unsigned int channel, unsigned int *sample);
|
||||
|
||||
void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
|
||||
|
||||
#define MC13783_SW_SW1A 0
|
||||
#define MC13783_SW_SW1B 1
|
||||
|
|
@ -80,5 +109,46 @@ void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
|
|||
#define MC13783_REGU_V3 29
|
||||
#define MC13783_REGU_V4 30
|
||||
|
||||
#endif /* __INCLUDE_LINUX_MFD_MC13783_H */
|
||||
#define MC13783_IRQ_ADCDONE 0
|
||||
#define MC13783_IRQ_ADCBISDONE 1
|
||||
#define MC13783_IRQ_TS 2
|
||||
#define MC13783_IRQ_WHIGH 3
|
||||
#define MC13783_IRQ_WLOW 4
|
||||
#define MC13783_IRQ_CHGDET 6
|
||||
#define MC13783_IRQ_CHGOV 7
|
||||
#define MC13783_IRQ_CHGREV 8
|
||||
#define MC13783_IRQ_CHGSHORT 9
|
||||
#define MC13783_IRQ_CCCV 10
|
||||
#define MC13783_IRQ_CHGCURR 11
|
||||
#define MC13783_IRQ_BPON 12
|
||||
#define MC13783_IRQ_LOBATL 13
|
||||
#define MC13783_IRQ_LOBATH 14
|
||||
#define MC13783_IRQ_UDP 15
|
||||
#define MC13783_IRQ_USB 16
|
||||
#define MC13783_IRQ_ID 19
|
||||
#define MC13783_IRQ_SE1 21
|
||||
#define MC13783_IRQ_CKDET 22
|
||||
#define MC13783_IRQ_UDM 23
|
||||
#define MC13783_IRQ_1HZ 24
|
||||
#define MC13783_IRQ_TODA 25
|
||||
#define MC13783_IRQ_ONOFD1 27
|
||||
#define MC13783_IRQ_ONOFD2 28
|
||||
#define MC13783_IRQ_ONOFD3 29
|
||||
#define MC13783_IRQ_SYSRST 30
|
||||
#define MC13783_IRQ_RTCRST 31
|
||||
#define MC13783_IRQ_PC 32
|
||||
#define MC13783_IRQ_WARM 33
|
||||
#define MC13783_IRQ_MEMHLD 34
|
||||
#define MC13783_IRQ_PWRRDY 35
|
||||
#define MC13783_IRQ_THWARNL 36
|
||||
#define MC13783_IRQ_THWARNH 37
|
||||
#define MC13783_IRQ_CLK 38
|
||||
#define MC13783_IRQ_SEMAF 39
|
||||
#define MC13783_IRQ_MC2B 41
|
||||
#define MC13783_IRQ_HSDET 42
|
||||
#define MC13783_IRQ_HSL 43
|
||||
#define MC13783_IRQ_ALSPTH 44
|
||||
#define MC13783_IRQ_AHSSHORT 45
|
||||
#define MC13783_NUM_IRQ 46
|
||||
|
||||
#endif /* __LINUX_MFD_MC13783_H */
|
||||
|
|
|
|||
|
|
@ -40,10 +40,6 @@ struct pcf50633_platform_data {
|
|||
u8 resumers[5];
|
||||
};
|
||||
|
||||
struct pcf50633_subdev_pdata {
|
||||
struct pcf50633 *pcf;
|
||||
};
|
||||
|
||||
struct pcf50633_irq {
|
||||
void (*handler) (int, void *);
|
||||
void *data;
|
||||
|
|
@ -217,5 +213,9 @@ enum pcf50633_reg_int5 {
|
|||
#define PCF50633_REG_LEDCTL 0x2a
|
||||
#define PCF50633_REG_LEDDIM 0x2b
|
||||
|
||||
#endif
|
||||
static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
|
||||
{
|
||||
return dev_get_drvdata(dev);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
#define __MFD_WM831X_CORE_H__
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
/*
|
||||
* Register values.
|
||||
|
|
@ -117,6 +116,7 @@
|
|||
#define WM831X_DC3_SLEEP_CONTROL 0x4063
|
||||
#define WM831X_DC4_CONTROL 0x4064
|
||||
#define WM831X_DC4_SLEEP_CONTROL 0x4065
|
||||
#define WM832X_DC4_SLEEP_CONTROL 0x4067
|
||||
#define WM831X_EPE1_CONTROL 0x4066
|
||||
#define WM831X_EPE2_CONTROL 0x4067
|
||||
#define WM831X_LDO1_CONTROL 0x4068
|
||||
|
|
@ -235,6 +235,8 @@
|
|||
|
||||
struct regulator_dev;
|
||||
|
||||
#define WM831X_NUM_IRQ_REGS 5
|
||||
|
||||
struct wm831x {
|
||||
struct mutex io_lock;
|
||||
|
||||
|
|
@ -248,10 +250,11 @@ struct wm831x {
|
|||
|
||||
int irq; /* Our chip IRQ */
|
||||
struct mutex irq_lock;
|
||||
struct workqueue_struct *irq_wq;
|
||||
struct work_struct irq_work;
|
||||
unsigned int irq_base;
|
||||
int irq_masks[5];
|
||||
int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
|
||||
int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
|
||||
|
||||
int num_gpio;
|
||||
|
||||
struct mutex auxadc_lock;
|
||||
|
||||
|
|
@ -278,12 +281,30 @@ int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
|
|||
int wm831x_irq_init(struct wm831x *wm831x, int irq);
|
||||
void wm831x_irq_exit(struct wm831x *wm831x);
|
||||
|
||||
int __must_check wm831x_request_irq(struct wm831x *wm831x,
|
||||
unsigned int irq, irq_handler_t handler,
|
||||
unsigned long flags, const char *name,
|
||||
void *dev);
|
||||
void wm831x_free_irq(struct wm831x *wm831x, unsigned int, void *);
|
||||
void wm831x_disable_irq(struct wm831x *wm831x, int irq);
|
||||
void wm831x_enable_irq(struct wm831x *wm831x, int irq);
|
||||
static inline int __must_check wm831x_request_irq(struct wm831x *wm831x,
|
||||
unsigned int irq,
|
||||
irq_handler_t handler,
|
||||
unsigned long flags,
|
||||
const char *name,
|
||||
void *dev)
|
||||
{
|
||||
return request_threaded_irq(irq, NULL, handler, flags, name, dev);
|
||||
}
|
||||
|
||||
static inline void wm831x_free_irq(struct wm831x *wm831x,
|
||||
unsigned int irq, void *dev)
|
||||
{
|
||||
free_irq(irq, dev);
|
||||
}
|
||||
|
||||
static inline void wm831x_disable_irq(struct wm831x *wm831x, int irq)
|
||||
{
|
||||
disable_irq(irq);
|
||||
}
|
||||
|
||||
static inline void wm831x_enable_irq(struct wm831x *wm831x, int irq)
|
||||
{
|
||||
enable_irq(irq);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ struct wm831x_pdata {
|
|||
/** Called after subdevices are set up */
|
||||
int (*post_init)(struct wm831x *wm831x);
|
||||
|
||||
int irq_base;
|
||||
int gpio_base;
|
||||
struct wm831x_backlight_pdata *backlight;
|
||||
struct wm831x_backup_pdata *backup;
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <linux/mfd/wm8350/audio.h>
|
||||
#include <linux/mfd/wm8350/gpio.h>
|
||||
|
|
@ -601,7 +601,7 @@ extern const u16 wm8352_mode3_defaults[];
|
|||
struct wm8350;
|
||||
|
||||
struct wm8350_irq {
|
||||
void (*handler) (struct wm8350 *, int, void *);
|
||||
irq_handler_t handler;
|
||||
void *data;
|
||||
};
|
||||
|
||||
|
|
@ -646,10 +646,12 @@ struct wm8350 {
|
|||
* @init: Function called during driver initialisation. Should be
|
||||
* used by the platform to configure GPIO functions and similar.
|
||||
* @irq_high: Set if WM8350 IRQ is active high.
|
||||
* @irq_base: Base IRQ for genirq (not currently used).
|
||||
*/
|
||||
struct wm8350_platform_data {
|
||||
int (*init)(struct wm8350 *wm8350);
|
||||
int irq_high;
|
||||
int irq_base;
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -676,11 +678,13 @@ int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
|
|||
* WM8350 internal interrupts
|
||||
*/
|
||||
int wm8350_register_irq(struct wm8350 *wm8350, int irq,
|
||||
void (*handler) (struct wm8350 *, int, void *),
|
||||
void *data);
|
||||
irq_handler_t handler, unsigned long flags,
|
||||
const char *name, void *data);
|
||||
int wm8350_free_irq(struct wm8350 *wm8350, int irq);
|
||||
int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
|
||||
int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
|
||||
|
||||
int wm8350_irq_init(struct wm8350 *wm8350, int irq,
|
||||
struct wm8350_platform_data *pdata);
|
||||
int wm8350_irq_exit(struct wm8350 *wm8350);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -172,6 +172,24 @@
|
|||
#define WM8350_GPIO_DEBOUNCE_OFF 0
|
||||
#define WM8350_GPIO_DEBOUNCE_ON 1
|
||||
|
||||
/*
|
||||
* R30 (0x1E) - GPIO Interrupt Status
|
||||
*/
|
||||
#define WM8350_GP12_EINT 0x1000
|
||||
#define WM8350_GP11_EINT 0x0800
|
||||
#define WM8350_GP10_EINT 0x0400
|
||||
#define WM8350_GP9_EINT 0x0200
|
||||
#define WM8350_GP8_EINT 0x0100
|
||||
#define WM8350_GP7_EINT 0x0080
|
||||
#define WM8350_GP6_EINT 0x0040
|
||||
#define WM8350_GP5_EINT 0x0020
|
||||
#define WM8350_GP4_EINT 0x0010
|
||||
#define WM8350_GP3_EINT 0x0008
|
||||
#define WM8350_GP2_EINT 0x0004
|
||||
#define WM8350_GP1_EINT 0x0002
|
||||
#define WM8350_GP0_EINT 0x0001
|
||||
|
||||
|
||||
/*
|
||||
* R128 (0x80) - GPIO Debounce
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue