Merge tag 'drm-for-v4.9' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "Core: - Fence destaging work - DRIVER_LEGACY to split off legacy drm drivers - drm_mm refactoring - Splitting drm_crtc.c into chunks and documenting better - Display info fixes - rbtree support for prime buffer lookup - Simple VGA DAC driver Panel: - Add Nexus 7 panel - More simple panels i915: - Refactoring GEM naming - Refactored vma/active tracking - Lockless request lookups - Better stolen memory support - FBC fixes - SKL watermark fixes - VGPU improvements - dma-buf fencing support - Better DP dongle support amdgpu: - Powerplay for Iceland asics - Improved GPU reset support - UVD/VEC powergating support for CZ/ST - Preinitialised VRAM buffer support - Virtual display support - Initial SI support - GTT rework - PCI shutdown callback support - HPD IRQ storm fixes amdkfd: - bugfixes tilcdc: - Atomic modesetting support mediatek: - AAL + GAMMA engine support - Hook up gamma LUT - Temporal dithering support imx: - Pixel clock from devicetree - drm bridge support for LVDS bridges - active plane reconfiguration - VDIC deinterlacer support - Frame synchronisation unit support - Color space conversion support analogix: - PSR support - Better panel on/off support rockchip: - rk3399 vop/crtc support - PSR support vc4: - Interlaced vblank timing - 3D rendering CPU overhead reduction - HDMI output fixes tda998x: - HDMI audio ASoC support sunxi: - Allwinner A33 support - better TCON support msm: - DT binding cleanups - Explicit fence-fd support sti: - remove sti415/416 support etnaviv: - MMUv2 refactoring - GC3000 support exynos: - Refactoring HDMI DCC/PHY - G2D pm regression fix - Page fault issues with wait for vblank There is no nouveau work in this tree, as Ben didn't get a pull request in, and he was fighting moving to atomic and adding mst support, so maybe best it waits for a cycle" * tag 'drm-for-v4.9' of git://people.freedesktop.org/~airlied/linux: (1412 commits) drm/crtc: constify drm_crtc_index parameter drm/i915: Fix conflict resolution from backmerge of v4.8-rc8 to drm-next drm/i915/guc: Unwind GuC workqueue reservation if request construction fails drm/i915: Reset the breadcrumbs IRQ more carefully drm/i915: Force relocations via cpu if we run out of idle aperture drm/i915: Distinguish last emitted request from last submitted request drm/i915: Allow DP to work w/o EDID drm/i915: Move long hpd handling into the hotplug work drm/i915/execlists: Reinitialise context image after GPU hang drm/i915: Use correct index for backtracking HUNG semaphores drm/i915: Unalias obj->phys_handle and obj->userptr drm/i915: Just clear the mmiodebug before a register access drm/i915/gen9: only add the planes actually affected by ddb changes drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED drm/i915/bxt: Fix HDMI DPLL configuration drm/i915/gen9: fix the watermark res_blocks value drm/i915/gen9: fix plane_blocks_per_line on watermarks calculations drm/i915/gen9: minimum scanlines for Y tile is not always 4 drm/i915/gen9: fix the WaWmMemoryReadLatency implementation drm/i915/kbl: KBL also needs to run the SAGV code ...
This commit is contained in:
Linus Torvalds
commit
6b25e21fa6
682 changed files with 85208 additions and 54298 deletions
|
|
@ -77,6 +77,10 @@ extern "C" {
|
|||
#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
|
||||
/* Flag that USWC attributes should be used for GTT */
|
||||
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
|
||||
/* Flag that the memory should be in VRAM and cleared */
|
||||
#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
|
||||
/* Flag that create shadow bo(GTT) while allocating vram bo */
|
||||
#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
|
||||
|
||||
struct drm_amdgpu_gem_create_in {
|
||||
/** the requested memory size */
|
||||
|
|
@ -481,6 +485,8 @@ struct drm_amdgpu_cs_chunk_data {
|
|||
#define AMDGPU_INFO_DEV_INFO 0x16
|
||||
/* visible vram usage */
|
||||
#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
|
||||
/* number of TTM buffer evictions */
|
||||
#define AMDGPU_INFO_NUM_EVICTIONS 0x18
|
||||
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
|
||||
|
|
@ -643,6 +649,7 @@ struct drm_amdgpu_info_hw_ip {
|
|||
* Supported GPU families
|
||||
*/
|
||||
#define AMDGPU_FAMILY_UNKNOWN 0
|
||||
#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
|
||||
#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
|
||||
#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
|
||||
#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
|
||||
|
|
|
|||
|
|
@ -646,6 +646,7 @@ struct drm_gem_open {
|
|||
#define DRM_CAP_CURSOR_WIDTH 0x8
|
||||
#define DRM_CAP_CURSOR_HEIGHT 0x9
|
||||
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
|
||||
#define DRM_CAP_PAGE_FLIP_TARGET 0x11
|
||||
|
||||
/** DRM_IOCTL_GET_CAP ioctl argument type */
|
||||
struct drm_get_cap {
|
||||
|
|
|
|||
|
|
@ -520,7 +520,13 @@ struct drm_color_lut {
|
|||
|
||||
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
|
||||
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
|
||||
#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
|
||||
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
|
||||
#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
|
||||
#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \
|
||||
DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
|
||||
#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \
|
||||
DRM_MODE_PAGE_FLIP_ASYNC | \
|
||||
DRM_MODE_PAGE_FLIP_TARGET)
|
||||
|
||||
/*
|
||||
* Request a page flip on the specified crtc.
|
||||
|
|
@ -543,8 +549,7 @@ struct drm_color_lut {
|
|||
* 'as soon as possible', meaning that it not delay waiting for vblank.
|
||||
* This may cause tearing on the screen.
|
||||
*
|
||||
* The reserved field must be zero until we figure out something
|
||||
* clever to use it for.
|
||||
* The reserved field must be zero.
|
||||
*/
|
||||
|
||||
struct drm_mode_crtc_page_flip {
|
||||
|
|
@ -555,6 +560,34 @@ struct drm_mode_crtc_page_flip {
|
|||
__u64 user_data;
|
||||
};
|
||||
|
||||
/*
|
||||
* Request a page flip on the specified crtc.
|
||||
*
|
||||
* Same as struct drm_mode_crtc_page_flip, but supports new flags and
|
||||
* re-purposes the reserved field:
|
||||
*
|
||||
* The sequence field must be zero unless either of the
|
||||
* DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is specified. When
|
||||
* the ABSOLUTE flag is specified, the sequence field denotes the absolute
|
||||
* vblank sequence when the flip should take effect. When the RELATIVE
|
||||
* flag is specified, the sequence field denotes the relative (to the
|
||||
* current one when the ioctl is called) vblank sequence when the flip
|
||||
* should take effect. NOTE: DRM_IOCTL_WAIT_VBLANK must still be used to
|
||||
* make sure the vblank sequence before the target one has passed before
|
||||
* calling this ioctl. The purpose of the
|
||||
* DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is merely to clarify
|
||||
* the target for when code dealing with a page flip runs during a
|
||||
* vertical blank period.
|
||||
*/
|
||||
|
||||
struct drm_mode_crtc_page_flip_target {
|
||||
__u32 crtc_id;
|
||||
__u32 fb_id;
|
||||
__u32 flags;
|
||||
__u32 sequence;
|
||||
__u64 user_data;
|
||||
};
|
||||
|
||||
/* create a dumb scanout buffer */
|
||||
struct drm_mode_create_dumb {
|
||||
__u32 height;
|
||||
|
|
|
|||
|
|
@ -62,6 +62,30 @@ extern "C" {
|
|||
#define I915_ERROR_UEVENT "ERROR"
|
||||
#define I915_RESET_UEVENT "RESET"
|
||||
|
||||
/*
|
||||
* MOCS indexes used for GPU surfaces, defining the cacheability of the
|
||||
* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
|
||||
*/
|
||||
enum i915_mocs_table_index {
|
||||
/*
|
||||
* Not cached anywhere, coherency between CPU and GPU accesses is
|
||||
* guaranteed.
|
||||
*/
|
||||
I915_MOCS_UNCACHED,
|
||||
/*
|
||||
* Cacheability and coherency controlled by the kernel automatically
|
||||
* based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
|
||||
* usage of the surface (used for display scanout or not).
|
||||
*/
|
||||
I915_MOCS_PTE,
|
||||
/*
|
||||
* Cached in all GPU caches available on the platform.
|
||||
* Coherency between CPU and GPU accesses to the surface is not
|
||||
* guaranteed without extra synchronization.
|
||||
*/
|
||||
I915_MOCS_CACHED,
|
||||
};
|
||||
|
||||
/* Each region is a minimum of 16k, and there are at most 255 of them.
|
||||
*/
|
||||
#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
|
||||
|
|
@ -363,6 +387,7 @@ typedef struct drm_i915_irq_wait {
|
|||
#define I915_PARAM_HAS_EXEC_SOFTPIN 37
|
||||
#define I915_PARAM_HAS_POOLED_EU 38
|
||||
#define I915_PARAM_MIN_EU_IN_POOL 39
|
||||
#define I915_PARAM_MMAP_GTT_VERSION 40
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
__s32 param;
|
||||
|
|
@ -698,15 +723,20 @@ struct drm_i915_gem_exec_object2 {
|
|||
*/
|
||||
__u64 offset;
|
||||
|
||||
#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
|
||||
#define EXEC_OBJECT_NEEDS_GTT (1<<1)
|
||||
#define EXEC_OBJECT_WRITE (1<<2)
|
||||
#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
|
||||
#define EXEC_OBJECT_NEEDS_GTT (1<<1)
|
||||
#define EXEC_OBJECT_WRITE (1<<2)
|
||||
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
|
||||
#define EXEC_OBJECT_PINNED (1<<4)
|
||||
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
|
||||
#define EXEC_OBJECT_PINNED (1<<4)
|
||||
#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
|
||||
/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
|
||||
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PAD_TO_SIZE<<1)
|
||||
__u64 flags;
|
||||
|
||||
__u64 rsvd1;
|
||||
union {
|
||||
__u64 rsvd1;
|
||||
__u64 pad_to_size;
|
||||
};
|
||||
__u64 rsvd2;
|
||||
};
|
||||
|
||||
|
|
@ -826,7 +856,16 @@ struct drm_i915_gem_busy {
|
|||
* having flushed any pending activity), and a non-zero return that
|
||||
* the object is still in-flight on the GPU. (The GPU has not yet
|
||||
* signaled completion for all pending requests that reference the
|
||||
* object.)
|
||||
* object.) An object is guaranteed to become idle eventually (so
|
||||
* long as no new GPU commands are executed upon it). Due to the
|
||||
* asynchronous nature of the hardware, an object reported
|
||||
* as busy may become idle before the ioctl is completed.
|
||||
*
|
||||
* Furthermore, if the object is busy, which engine is busy is only
|
||||
* provided as a guide. There are race conditions which prevent the
|
||||
* report of which engines are busy from being always accurate.
|
||||
* However, the converse is not true. If the object is idle, the
|
||||
* result of the ioctl, that all engines are idle, is accurate.
|
||||
*
|
||||
* The returned dword is split into two fields to indicate both
|
||||
* the engines on which the object is being read, and the
|
||||
|
|
@ -849,6 +888,11 @@ struct drm_i915_gem_busy {
|
|||
* execution engines, e.g. multiple media engines, which are
|
||||
* mapped to the same identifier in the EXECBUFFER2 ioctl and
|
||||
* so are not separately reported for busyness.
|
||||
*
|
||||
* Caveat emptor:
|
||||
* Only the boolean result of this query is reliable; that is whether
|
||||
* the object is idle or busy. The report of which engines are busy
|
||||
* should be only used as a heuristic.
|
||||
*/
|
||||
__u32 busy;
|
||||
};
|
||||
|
|
@ -897,6 +941,7 @@ struct drm_i915_gem_caching {
|
|||
#define I915_TILING_NONE 0
|
||||
#define I915_TILING_X 1
|
||||
#define I915_TILING_Y 2
|
||||
#define I915_TILING_LAST I915_TILING_Y
|
||||
|
||||
#define I915_BIT_6_SWIZZLE_NONE 0
|
||||
#define I915_BIT_6_SWIZZLE_9 1
|
||||
|
|
|
|||
|
|
@ -42,6 +42,15 @@ extern "C" {
|
|||
#define MSM_PIPE_2D1 0x02
|
||||
#define MSM_PIPE_3D0 0x10
|
||||
|
||||
/* The pipe-id just uses the lower bits, so can be OR'd with flags in
|
||||
* the upper 16 bits (which could be extended further, if needed, maybe
|
||||
* we extend/overload the pipe-id some day to deal with multiple rings,
|
||||
* but even then I don't think we need the full lower 16 bits).
|
||||
*/
|
||||
#define MSM_PIPE_ID_MASK 0xffff
|
||||
#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
|
||||
#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
|
||||
|
||||
/* timeouts are specified in clock-monotonic absolute times (to simplify
|
||||
* restarting interrupted ioctls). The following struct is logically the
|
||||
* same as 'struct timespec' but 32/64b ABI safe.
|
||||
|
|
@ -175,17 +184,28 @@ struct drm_msm_gem_submit_bo {
|
|||
__u64 presumed; /* in/out, presumed buffer address */
|
||||
};
|
||||
|
||||
/* Valid submit ioctl flags: */
|
||||
#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
|
||||
#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
|
||||
#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
|
||||
#define MSM_SUBMIT_FLAGS ( \
|
||||
MSM_SUBMIT_NO_IMPLICIT | \
|
||||
MSM_SUBMIT_FENCE_FD_IN | \
|
||||
MSM_SUBMIT_FENCE_FD_OUT | \
|
||||
0)
|
||||
|
||||
/* Each cmdstream submit consists of a table of buffers involved, and
|
||||
* one or more cmdstream buffers. This allows for conditional execution
|
||||
* (context-restore), and IB buffers needed for per tile/bin draw cmds.
|
||||
*/
|
||||
struct drm_msm_gem_submit {
|
||||
__u32 pipe; /* in, MSM_PIPE_x */
|
||||
__u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
|
||||
__u32 fence; /* out */
|
||||
__u32 nr_bos; /* in, number of submit_bo's */
|
||||
__u32 nr_cmds; /* in, number of submit_cmd's */
|
||||
__u64 __user bos; /* in, ptr to array of submit_bo's */
|
||||
__u64 __user cmds; /* in, ptr to array of submit_cmd's */
|
||||
__s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
|
||||
};
|
||||
|
||||
/* The normal way to synchronize with the GPU is just to CPU_PREP on
|
||||
|
|
|
|||
|
|
@ -399,6 +399,7 @@ header-y += string.h
|
|||
header-y += suspend_ioctls.h
|
||||
header-y += swab.h
|
||||
header-y += synclink.h
|
||||
header-y += sync_file.h
|
||||
header-y += sysctl.h
|
||||
header-y += sysinfo.h
|
||||
header-y += target_core_user.h
|
||||
|
|
|
|||
|
|
@ -85,15 +85,12 @@ struct sync_file_info {
|
|||
#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 3, struct sync_merge_data)
|
||||
|
||||
/**
|
||||
* DOC: SYNC_IOC_FENCE_INFO - get detailed information on a fence
|
||||
* DOC: SYNC_IOC_FILE_INFO - get detailed information on a sync_file
|
||||
*
|
||||
* Takes a struct sync_file_info_data with extra space allocated for pt_info.
|
||||
* Caller should write the size of the buffer into len. On return, len is
|
||||
* updated to reflect the total size of the sync_file_info_data including
|
||||
* pt_info.
|
||||
*
|
||||
* pt_info is a buffer containing sync_pt_infos for every sync_pt in the fence.
|
||||
* To iterate over the sync_pt_infos, use the sync_pt_info.len field.
|
||||
* Takes a struct sync_file_info. If num_fences is 0, the field is updated
|
||||
* with the actual number of fences. If num_fences is > 0, the system will
|
||||
* use the pointer provided on sync_fence_info to return up to num_fences of
|
||||
* struct sync_fence_info, with detailed fence information.
|
||||
*/
|
||||
#define SYNC_IOC_FILE_INFO _IOWR(SYNC_IOC_MAGIC, 4, struct sync_file_info)
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue