dmaengine: coh901318: Split device_control
Split the device_control callback of the ST-Ericsson COH901318 DMA driver to make use of the newly introduced callbacks, that will eventually be used to retrieve slave capabilities. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Maxime Ripard
Vinod Koul
parent
39159bea78
commit
6782af118b
1 changed files with 60 additions and 77 deletions
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@ -2114,6 +2114,57 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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static int coh901318_terminate_all(struct dma_chan *chan)
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{
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unsigned long flags;
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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struct coh901318_desc *cohd;
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void __iomem *virtbase = cohc->base->virtbase;
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/* The remainder of this function terminates the transfer */
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coh901318_pause(chan);
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spin_lock_irqsave(&cohc->lock, flags);
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/* Clear any pending BE or TC interrupt */
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if (cohc->id < 32) {
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writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
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writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
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} else {
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writel(1 << (cohc->id - 32), virtbase +
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COH901318_BE_INT_CLEAR2);
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writel(1 << (cohc->id - 32), virtbase +
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COH901318_TC_INT_CLEAR2);
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}
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enable_powersave(cohc);
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while ((cohd = coh901318_first_active_get(cohc))) {
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/* release the lli allocation*/
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coh901318_lli_free(&cohc->base->pool, &cohd->lli);
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/* return desc to free-list */
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coh901318_desc_remove(cohd);
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coh901318_desc_free(cohc, cohd);
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}
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while ((cohd = coh901318_first_queued(cohc))) {
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/* release the lli allocation*/
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coh901318_lli_free(&cohc->base->pool, &cohd->lli);
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/* return desc to free-list */
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coh901318_desc_remove(cohd);
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coh901318_desc_free(cohc, cohd);
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}
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cohc->nbr_active_done = 0;
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cohc->busy = 0;
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spin_unlock_irqrestore(&cohc->lock, flags);
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return 0;
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}
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static int coh901318_alloc_chan_resources(struct dma_chan *chan)
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static int coh901318_alloc_chan_resources(struct dma_chan *chan)
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{
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{
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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@ -2156,7 +2207,7 @@ coh901318_free_chan_resources(struct dma_chan *chan)
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spin_unlock_irqrestore(&cohc->lock, flags);
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spin_unlock_irqrestore(&cohc->lock, flags);
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dmaengine_terminate_all(chan);
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coh901318_terminate_all(chan);
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}
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}
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@ -2540,80 +2591,6 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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cohc->ctrl = ctrl;
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cohc->ctrl = ctrl;
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}
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}
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static int
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coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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{
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unsigned long flags;
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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struct coh901318_desc *cohd;
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void __iomem *virtbase = cohc->base->virtbase;
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if (cmd == DMA_SLAVE_CONFIG) {
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struct dma_slave_config *config =
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(struct dma_slave_config *) arg;
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coh901318_dma_set_runtimeconfig(chan, config);
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return 0;
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}
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if (cmd == DMA_PAUSE) {
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coh901318_pause(chan);
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return 0;
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}
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if (cmd == DMA_RESUME) {
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coh901318_resume(chan);
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return 0;
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}
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if (cmd != DMA_TERMINATE_ALL)
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return -ENXIO;
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/* The remainder of this function terminates the transfer */
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coh901318_pause(chan);
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spin_lock_irqsave(&cohc->lock, flags);
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/* Clear any pending BE or TC interrupt */
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if (cohc->id < 32) {
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writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
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writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
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} else {
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writel(1 << (cohc->id - 32), virtbase +
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COH901318_BE_INT_CLEAR2);
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writel(1 << (cohc->id - 32), virtbase +
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COH901318_TC_INT_CLEAR2);
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}
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enable_powersave(cohc);
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while ((cohd = coh901318_first_active_get(cohc))) {
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/* release the lli allocation*/
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coh901318_lli_free(&cohc->base->pool, &cohd->lli);
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/* return desc to free-list */
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coh901318_desc_remove(cohd);
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coh901318_desc_free(cohc, cohd);
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}
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while ((cohd = coh901318_first_queued(cohc))) {
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/* release the lli allocation*/
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coh901318_lli_free(&cohc->base->pool, &cohd->lli);
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/* return desc to free-list */
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coh901318_desc_remove(cohd);
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coh901318_desc_free(cohc, cohd);
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}
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cohc->nbr_active_done = 0;
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cohc->busy = 0;
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spin_unlock_irqrestore(&cohc->lock, flags);
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return 0;
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}
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void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
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void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
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struct coh901318_base *base)
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struct coh901318_base *base)
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{
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{
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@ -2717,7 +2694,10 @@ static int __init coh901318_probe(struct platform_device *pdev)
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base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
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base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
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base->dma_slave.device_tx_status = coh901318_tx_status;
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base->dma_slave.device_tx_status = coh901318_tx_status;
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base->dma_slave.device_issue_pending = coh901318_issue_pending;
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base->dma_slave.device_issue_pending = coh901318_issue_pending;
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base->dma_slave.device_control = coh901318_control;
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base->dma_slave.device_config = coh901318_dma_set_runtimeconfig;
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base->dma_slave.device_pause = coh901318_pause;
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base->dma_slave.device_resume = coh901318_resume;
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base->dma_slave.device_terminate_all = coh901318_terminate_all;
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base->dma_slave.dev = &pdev->dev;
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base->dma_slave.dev = &pdev->dev;
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err = dma_async_device_register(&base->dma_slave);
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err = dma_async_device_register(&base->dma_slave);
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@ -2737,7 +2717,10 @@ static int __init coh901318_probe(struct platform_device *pdev)
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base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
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base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
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base->dma_memcpy.device_tx_status = coh901318_tx_status;
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base->dma_memcpy.device_tx_status = coh901318_tx_status;
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base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
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base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
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base->dma_memcpy.device_control = coh901318_control;
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base->dma_memcpy.device_config = coh901318_dma_set_runtimeconfig;
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base->dma_memcpy.device_pause = coh901318_pause;
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base->dma_memcpy.device_resume = coh901318_resume;
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base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
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base->dma_memcpy.dev = &pdev->dev;
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base->dma_memcpy.dev = &pdev->dev;
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/*
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/*
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* This controller can only access address at even 32bit boundaries,
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* This controller can only access address at even 32bit boundaries,
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