Merge branch 'drm-next-merged' of git://people.freedesktop.org/~airlied/linux into v4l_for_linus
* 'drm-next-merged' of git://people.freedesktop.org/~airlied/linux: (9717 commits) media-bus: Fixup RGB444_1X12, RGB565_1X16, and YUV8_1X24 media bus format hexdump: avoid warning in test function fs: take i_mutex during prepare_binprm for set[ug]id executables smp: Fix error case handling in smp_call_function_*() iommu-common: Fix PARISC compile-time warnings sparc: Make LDC use common iommu poll management functions sparc: Make sparc64 use scalable lib/iommu-common.c functions Break up monolithic iommu table/lock into finer graularity pools and lock sparc: Revert generic IOMMU allocator. tools/power turbostat: correct dumped pkg-cstate-limit value tools/power turbostat: calculate TSC frequency from CPUID(0x15) on SKL tools/power turbostat: correct DRAM RAPL units on recent Xeon processors tools/power turbostat: Initial Skylake support tools/power turbostat: Use $(CURDIR) instead of $(PWD) and add support for O= option in Makefile tools/power turbostat: modprobe msr, if needed tools/power turbostat: dump MSR_TURBO_RATIO_LIMIT2 tools/power turbostat: use new MSR_TURBO_RATIO_LIMIT names Bluetooth: hidp: Fix regression with older userspace and flags validation config: Enable NEED_DMA_MAP_STATE by default when SWIOTLB is selected perf/x86/intel/pt: Fix and clean up error handling in pt_event_add() ... That solves several merge conflicts: Documentation/DocBook/media/v4l/subdev-formats.xml Documentation/devicetree/bindings/vendor-prefixes.txt drivers/staging/media/mn88473/mn88473.c include/linux/kconfig.h include/uapi/linux/media-bus-format.h The ones at subdev-formats.xml and media-bus-format.h are not trivial. That's why we opted to merge from DRM.
This commit is contained in:
Mauro Carvalho Chehab
commit
64131a87f2
7787 changed files with 315977 additions and 156363 deletions
183
include/dt-bindings/clock/pistachio-clk.h
Normal file
183
include/dt-bindings/clock/pistachio-clk.h
Normal file
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@ -0,0 +1,183 @@
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|||
/*
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||||
* Copyright (C) 2014 Google, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H
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#define _DT_BINDINGS_CLOCK_PISTACHIO_H
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/* PLLs */
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#define CLK_MIPS_PLL 0
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#define CLK_AUDIO_PLL 1
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#define CLK_RPU_V_PLL 2
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#define CLK_RPU_L_PLL 3
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#define CLK_SYS_PLL 4
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#define CLK_WIFI_PLL 5
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#define CLK_BT_PLL 6
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/* Fixed-factor clocks */
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#define CLK_WIFI_DIV4 16
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#define CLK_WIFI_DIV8 17
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/* Gate clocks */
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#define CLK_MIPS 32
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#define CLK_AUDIO_IN 33
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#define CLK_AUDIO 34
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#define CLK_I2S 35
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#define CLK_SPDIF 36
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#define CLK_AUDIO_DAC 37
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#define CLK_RPU_V 38
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#define CLK_RPU_L 39
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#define CLK_RPU_SLEEP 40
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#define CLK_WIFI_PLL_GATE 41
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#define CLK_RPU_CORE 42
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#define CLK_WIFI_ADC 43
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#define CLK_WIFI_DAC 44
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#define CLK_USB_PHY 45
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#define CLK_ENET_IN 46
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#define CLK_ENET 47
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#define CLK_UART0 48
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#define CLK_UART1 49
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#define CLK_PERIPH_SYS 50
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#define CLK_SPI0 51
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#define CLK_SPI1 52
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#define CLK_EVENT_TIMER 53
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#define CLK_AUX_ADC_INTERNAL 54
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#define CLK_AUX_ADC 55
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#define CLK_SD_HOST 56
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#define CLK_BT 57
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#define CLK_BT_DIV4 58
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#define CLK_BT_DIV8 59
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#define CLK_BT_1MHZ 60
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/* Divider clocks */
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#define CLK_MIPS_INTERNAL_DIV 64
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#define CLK_MIPS_DIV 65
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#define CLK_AUDIO_DIV 66
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#define CLK_I2S_DIV 67
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#define CLK_SPDIF_DIV 68
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#define CLK_AUDIO_DAC_DIV 69
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#define CLK_RPU_V_DIV 70
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#define CLK_RPU_L_DIV 71
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#define CLK_RPU_SLEEP_DIV 72
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#define CLK_RPU_CORE_DIV 73
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#define CLK_USB_PHY_DIV 74
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#define CLK_ENET_DIV 75
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#define CLK_UART0_INTERNAL_DIV 76
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#define CLK_UART0_DIV 77
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#define CLK_UART1_INTERNAL_DIV 78
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#define CLK_UART1_DIV 79
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#define CLK_SYS_INTERNAL_DIV 80
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#define CLK_SPI0_INTERNAL_DIV 81
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#define CLK_SPI0_DIV 82
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#define CLK_SPI1_INTERNAL_DIV 83
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#define CLK_SPI1_DIV 84
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#define CLK_EVENT_TIMER_INTERNAL_DIV 85
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#define CLK_EVENT_TIMER_DIV 86
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#define CLK_AUX_ADC_INTERNAL_DIV 87
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#define CLK_AUX_ADC_DIV 88
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#define CLK_SD_HOST_DIV 89
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#define CLK_BT_DIV 90
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#define CLK_BT_DIV4_DIV 91
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#define CLK_BT_DIV8_DIV 92
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#define CLK_BT_1MHZ_INTERNAL_DIV 93
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#define CLK_BT_1MHZ_DIV 94
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|
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/* Mux clocks */
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#define CLK_AUDIO_REF_MUX 96
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#define CLK_MIPS_PLL_MUX 97
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#define CLK_AUDIO_PLL_MUX 98
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#define CLK_AUDIO_MUX 99
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#define CLK_RPU_V_PLL_MUX 100
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#define CLK_RPU_L_PLL_MUX 101
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#define CLK_RPU_L_MUX 102
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#define CLK_WIFI_PLL_MUX 103
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#define CLK_WIFI_DIV4_MUX 104
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#define CLK_WIFI_DIV8_MUX 105
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#define CLK_RPU_CORE_MUX 106
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#define CLK_SYS_PLL_MUX 107
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#define CLK_ENET_MUX 108
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#define CLK_EVENT_TIMER_MUX 109
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#define CLK_SD_HOST_MUX 110
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#define CLK_BT_PLL_MUX 111
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#define CLK_DEBUG_MUX 112
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#define CLK_NR_CLKS 113
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/* Peripheral gate clocks */
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#define PERIPH_CLK_SYS 0
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#define PERIPH_CLK_SYS_BUS 1
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#define PERIPH_CLK_DDR 2
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#define PERIPH_CLK_ROM 3
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#define PERIPH_CLK_COUNTER_FAST 4
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#define PERIPH_CLK_COUNTER_SLOW 5
|
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#define PERIPH_CLK_IR 6
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#define PERIPH_CLK_WD 7
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#define PERIPH_CLK_PDM 8
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#define PERIPH_CLK_PWM 9
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#define PERIPH_CLK_I2C0 10
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#define PERIPH_CLK_I2C1 11
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#define PERIPH_CLK_I2C2 12
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#define PERIPH_CLK_I2C3 13
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|
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/* Peripheral divider clocks */
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#define PERIPH_CLK_ROM_DIV 32
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#define PERIPH_CLK_COUNTER_FAST_DIV 33
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#define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34
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#define PERIPH_CLK_COUNTER_SLOW_DIV 35
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#define PERIPH_CLK_IR_PRE_DIV 36
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#define PERIPH_CLK_IR_DIV 37
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||||
#define PERIPH_CLK_WD_PRE_DIV 38
|
||||
#define PERIPH_CLK_WD_DIV 39
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#define PERIPH_CLK_PDM_PRE_DIV 40
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#define PERIPH_CLK_PDM_DIV 41
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#define PERIPH_CLK_PWM_PRE_DIV 42
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#define PERIPH_CLK_PWM_DIV 43
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#define PERIPH_CLK_I2C0_PRE_DIV 44
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#define PERIPH_CLK_I2C0_DIV 45
|
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#define PERIPH_CLK_I2C1_PRE_DIV 46
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#define PERIPH_CLK_I2C1_DIV 47
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#define PERIPH_CLK_I2C2_PRE_DIV 48
|
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#define PERIPH_CLK_I2C2_DIV 49
|
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#define PERIPH_CLK_I2C3_PRE_DIV 50
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#define PERIPH_CLK_I2C3_DIV 51
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#define PERIPH_CLK_NR_CLKS 52
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/* System gate clocks */
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#define SYS_CLK_I2C0 0
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#define SYS_CLK_I2C1 1
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#define SYS_CLK_I2C2 2
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#define SYS_CLK_I2C3 3
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#define SYS_CLK_I2S_IN 4
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#define SYS_CLK_PAUD_OUT 5
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#define SYS_CLK_SPDIF_OUT 6
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#define SYS_CLK_SPI0_MASTER 7
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#define SYS_CLK_SPI0_SLAVE 8
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#define SYS_CLK_PWM 9
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#define SYS_CLK_UART0 10
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#define SYS_CLK_UART1 11
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#define SYS_CLK_SPI1 12
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#define SYS_CLK_MDC 13
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#define SYS_CLK_SD_HOST 14
|
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#define SYS_CLK_ENET 15
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#define SYS_CLK_IR 16
|
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#define SYS_CLK_WD 17
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#define SYS_CLK_TIMER 18
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#define SYS_CLK_I2S_OUT 24
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#define SYS_CLK_SPDIF_IN 25
|
||||
#define SYS_CLK_EVENT_TIMER 26
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||||
#define SYS_CLK_HASH 27
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#define SYS_CLK_NR_CLKS 28
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|
||||
/* Gates for external input clocks */
|
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#define EXT_CLK_AUDIO_IN 0
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#define EXT_CLK_ENET_IN 1
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#define EXT_CLK_NR_CLKS 2
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|
||||
#endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */
|
||||
32
include/dt-bindings/gpio/meson8b-gpio.h
Normal file
32
include/dt-bindings/gpio/meson8b-gpio.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
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* GPIO definitions for Amlogic Meson8b SoCs
|
||||
*
|
||||
* Copyright (C) 2015 Endless Mobile, Inc.
|
||||
* Author: Carlo Caione <carlo@endlessm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON8B_GPIO_H
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#define _DT_BINDINGS_MESON8B_GPIO_H
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#include <dt-bindings/gpio/meson8-gpio.h>
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|
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/* GPIO Bank DIF */
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#define DIF_0_P 120
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#define DIF_0_N 121
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#define DIF_1_P 122
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#define DIF_1_N 123
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#define DIF_2_P 124
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#define DIF_2_N 125
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#define DIF_3_P 126
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#define DIF_3_N 127
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#define DIF_4_P 128
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#define DIF_4_N 129
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#endif /* _DT_BINDINGS_MESON8B_GPIO_H */
|
||||
30
include/dt-bindings/interrupt-controller/irq-st.h
Normal file
30
include/dt-bindings/interrupt-controller/irq-st.h
Normal file
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|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* include/linux/irqchip/irq-st.h
|
||||
*
|
||||
* Copyright (C) 2014 STMicroelectronics – All Rights Reserved
|
||||
*
|
||||
* Author: Lee Jones <lee.jones@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
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#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
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|
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#define ST_IRQ_SYSCFG_EXT_0 0
|
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#define ST_IRQ_SYSCFG_EXT_1 1
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#define ST_IRQ_SYSCFG_EXT_2 2
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#define ST_IRQ_SYSCFG_CTI_0 3
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#define ST_IRQ_SYSCFG_CTI_1 4
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#define ST_IRQ_SYSCFG_PMU_0 5
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#define ST_IRQ_SYSCFG_PMU_1 6
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#define ST_IRQ_SYSCFG_pl310_L2 7
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#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF
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#define ST_IRQ_SYSCFG_EXT_1_INV 0x1
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#define ST_IRQ_SYSCFG_EXT_2_INV 0x2
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#define ST_IRQ_SYSCFG_EXT_3_INV 0x4
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|
||||
#endif
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||||
21
include/dt-bindings/leds/common.h
Normal file
21
include/dt-bindings/leds/common.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* This header provides macros for the common LEDs device tree bindings.
|
||||
*
|
||||
* Copyright (C) 2015, Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Author: Jacek Anaszewski <j.anaszewski@samsung.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_LEDS_H__
|
||||
#define __DT_BINDINGS_LEDS_H
|
||||
|
||||
/* External trigger type */
|
||||
#define LEDS_TRIG_TYPE_EDGE 0
|
||||
#define LEDS_TRIG_TYPE_LEVEL 1
|
||||
|
||||
/* Boost modes */
|
||||
#define LEDS_BOOST_OFF 0
|
||||
#define LEDS_BOOST_ADAPTIVE 1
|
||||
#define LEDS_BOOST_FIXED 2
|
||||
|
||||
#endif /* __DT_BINDINGS_LEDS_H */
|
||||
93
include/dt-bindings/mfd/arizona.h
Normal file
93
include/dt-bindings/mfd/arizona.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Device Tree defines for Arizona devices
|
||||
*
|
||||
* Copyright 2015 Cirrus Logic Inc.
|
||||
*
|
||||
* Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MFD_ARIZONA_H
|
||||
#define _DT_BINDINGS_MFD_ARIZONA_H
|
||||
|
||||
/* GPIO Function Definitions */
|
||||
#define ARIZONA_GP_FN_TXLRCLK 0x00
|
||||
#define ARIZONA_GP_FN_GPIO 0x01
|
||||
#define ARIZONA_GP_FN_IRQ1 0x02
|
||||
#define ARIZONA_GP_FN_IRQ2 0x03
|
||||
#define ARIZONA_GP_FN_OPCLK 0x04
|
||||
#define ARIZONA_GP_FN_FLL1_OUT 0x05
|
||||
#define ARIZONA_GP_FN_FLL2_OUT 0x06
|
||||
#define ARIZONA_GP_FN_PWM1 0x08
|
||||
#define ARIZONA_GP_FN_PWM2 0x09
|
||||
#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A
|
||||
#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B
|
||||
#define ARIZONA_GP_FN_FLL1_LOCK 0x0C
|
||||
#define ARIZONA_GP_FN_FLL2_LOCK 0x0D
|
||||
#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F
|
||||
#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10
|
||||
#define ARIZONA_GP_FN_HEADPHONE_DET 0x12
|
||||
#define ARIZONA_GP_FN_MIC_DET 0x13
|
||||
#define ARIZONA_GP_FN_WSEQ_STATUS 0x15
|
||||
#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16
|
||||
#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A
|
||||
#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B
|
||||
#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C
|
||||
#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D
|
||||
#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E
|
||||
#define ARIZONA_GP_FN_DRC1_DECAY 0x1F
|
||||
#define ARIZONA_GP_FN_DRC1_NOISE 0x20
|
||||
#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21
|
||||
#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22
|
||||
#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23
|
||||
#define ARIZONA_GP_FN_DRC2_DECAY 0x24
|
||||
#define ARIZONA_GP_FN_DRC2_NOISE 0x25
|
||||
#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26
|
||||
#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27
|
||||
#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28
|
||||
#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29
|
||||
#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A
|
||||
#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B
|
||||
#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C
|
||||
#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D
|
||||
#define ARIZONA_GP_FN_OVERCLOCKED 0x2E
|
||||
#define ARIZONA_GP_FN_DSP_IRQ1 0x35
|
||||
#define ARIZONA_GP_FN_DSP_IRQ2 0x36
|
||||
#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D
|
||||
#define ARIZONA_GP_FN_BOOT_DONE 0x44
|
||||
#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45
|
||||
#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B
|
||||
#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C
|
||||
|
||||
/* GPIO Configuration Bits */
|
||||
#define ARIZONA_GPN_DIR 0x8000
|
||||
#define ARIZONA_GPN_PU 0x4000
|
||||
#define ARIZONA_GPN_PD 0x2000
|
||||
#define ARIZONA_GPN_LVL 0x0800
|
||||
#define ARIZONA_GPN_POL 0x0400
|
||||
#define ARIZONA_GPN_OP_CFG 0x0200
|
||||
#define ARIZONA_GPN_DB 0x0100
|
||||
|
||||
/* Provide some defines for the most common configs */
|
||||
#define ARIZONA_GP_DEFAULT 0xffffffff
|
||||
#define ARIZONA_GP_OUTPUT (ARIZONA_GP_FN_GPIO)
|
||||
#define ARIZONA_GP_INPUT (ARIZONA_GP_FN_GPIO | \
|
||||
ARIZONA_GPN_DIR)
|
||||
|
||||
#define ARIZONA_32KZ_MCLK1 1
|
||||
#define ARIZONA_32KZ_MCLK2 2
|
||||
#define ARIZONA_32KZ_NONE 3
|
||||
|
||||
#define ARIZONA_DMIC_MICVDD 0
|
||||
#define ARIZONA_DMIC_MICBIAS1 1
|
||||
#define ARIZONA_DMIC_MICBIAS2 2
|
||||
#define ARIZONA_DMIC_MICBIAS3 3
|
||||
|
||||
#define ARIZONA_INMODE_DIFF 0
|
||||
#define ARIZONA_INMODE_SE 1
|
||||
#define ARIZONA_INMODE_DMIC 2
|
||||
|
||||
#endif
|
||||
|
|
@ -141,6 +141,12 @@
|
|||
#define QCOM_RPM_SYS_FABRIC_MODE 131
|
||||
#define QCOM_RPM_USB_OTG_SWITCH 132
|
||||
#define QCOM_RPM_VDDMIN_GPIO 133
|
||||
#define QCOM_RPM_NSS_FABRIC_0_CLK 134
|
||||
#define QCOM_RPM_NSS_FABRIC_1_CLK 135
|
||||
#define QCOM_RPM_SMB208_S1a 136
|
||||
#define QCOM_RPM_SMB208_S1b 137
|
||||
#define QCOM_RPM_SMB208_S2a 138
|
||||
#define QCOM_RPM_SMB208_S2b 139
|
||||
|
||||
/*
|
||||
* Constants used to select force mode for regulators.
|
||||
|
|
|
|||
|
|
@ -1,14 +0,0 @@
|
|||
/*
|
||||
* This header provides constants for the phy framework
|
||||
* based on the STMicroelectronics MiPHY365x.
|
||||
*
|
||||
* Author: Lee Jones <lee.jones@linaro.org>
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_PHY_MIPHY
|
||||
#define _DT_BINDINGS_PHY_MIPHY
|
||||
|
||||
#define MIPHY_TYPE_SATA 1
|
||||
#define MIPHY_TYPE_PCIE 2
|
||||
#define MIPHY_TYPE_USB 3
|
||||
|
||||
#endif /* _DT_BINDINGS_PHY_MIPHY */
|
||||
|
|
@ -13,7 +13,8 @@
|
|||
|
||||
#define PULL_DISABLE (1 << 3)
|
||||
#define INPUT_EN (1 << 5)
|
||||
#define SLEWCTRL_FAST (1 << 6)
|
||||
#define SLEWCTRL_SLOW (1 << 6)
|
||||
#define SLEWCTRL_FAST 0
|
||||
|
||||
/* update macro depending on INPUT_EN and PULL_ENA */
|
||||
#undef PIN_OUTPUT
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@
|
|||
#define PULL_DISABLE (1 << 16)
|
||||
#define PULL_UP (1 << 17)
|
||||
#define INPUT_EN (1 << 18)
|
||||
#define SLEWCTRL_FAST (1 << 19)
|
||||
#define SLEWCTRL_SLOW (1 << 19)
|
||||
#define SLEWCTRL_FAST 0
|
||||
#define DS0_PULL_UP_DOWN_EN (1 << 27)
|
||||
|
||||
#define PIN_OUTPUT (PULL_DISABLE)
|
||||
|
|
|
|||
40
include/dt-bindings/pinctrl/mt65xx.h
Normal file
40
include/dt-bindings/pinctrl/mt65xx.h
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H
|
||||
#define _DT_BINDINGS_PINCTRL_MT65XX_H
|
||||
|
||||
#define MTK_PIN_NO(x) ((x) << 8)
|
||||
#define MTK_GET_PIN_NO(x) ((x) >> 8)
|
||||
#define MTK_GET_PIN_FUNC(x) ((x) & 0xf)
|
||||
|
||||
#define MTK_PUPD_SET_R1R0_00 100
|
||||
#define MTK_PUPD_SET_R1R0_01 101
|
||||
#define MTK_PUPD_SET_R1R0_10 102
|
||||
#define MTK_PUPD_SET_R1R0_11 103
|
||||
|
||||
#define MTK_DRIVE_2mA 2
|
||||
#define MTK_DRIVE_4mA 4
|
||||
#define MTK_DRIVE_6mA 6
|
||||
#define MTK_DRIVE_8mA 8
|
||||
#define MTK_DRIVE_10mA 10
|
||||
#define MTK_DRIVE_12mA 12
|
||||
#define MTK_DRIVE_14mA 14
|
||||
#define MTK_DRIVE_16mA 16
|
||||
#define MTK_DRIVE_20mA 20
|
||||
#define MTK_DRIVE_24mA 24
|
||||
#define MTK_DRIVE_28mA 28
|
||||
#define MTK_DRIVE_32mA 32
|
||||
|
||||
#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */
|
||||
|
|
@ -48,6 +48,14 @@
|
|||
#define PM8058_GPIO_L5 6
|
||||
#define PM8058_GPIO_L2 7
|
||||
|
||||
/*
|
||||
* Note: PM8916 GPIO1 and GPIO2 are supporting
|
||||
* only L2(1.15V) and L5(1.8V) options
|
||||
*/
|
||||
#define PM8916_GPIO_VPH 0
|
||||
#define PM8916_GPIO_L2 2
|
||||
#define PM8916_GPIO_L5 3
|
||||
|
||||
#define PM8917_GPIO_VPH 0
|
||||
#define PM8917_GPIO_S4 2
|
||||
#define PM8917_GPIO_L15 3
|
||||
|
|
@ -115,6 +123,13 @@
|
|||
#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1
|
||||
#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1
|
||||
|
||||
#define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
|
||||
#define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
|
||||
#define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1
|
||||
#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
|
||||
#define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1
|
||||
#define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
|
||||
|
||||
#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1
|
||||
#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
|
||||
#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
|
||||
|
|
|
|||
|
|
@ -10,6 +10,10 @@
|
|||
#define PM8841_MPP_VPH 0
|
||||
#define PM8841_MPP_S3 2
|
||||
|
||||
#define PM8916_MPP_VPH 0
|
||||
#define PM8916_MPP_L2 2
|
||||
#define PM8916_MPP_L5 3
|
||||
|
||||
#define PM8941_MPP_VPH 0
|
||||
#define PM8941_MPP_L1 1
|
||||
#define PM8941_MPP_S3 2
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue