ARM: i.MX5: Add PATA and SRTC clocks
This adds the clock gates and the binding documentation for PATA and SRTC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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			@ -183,6 +183,8 @@ clocks and IDs.
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	cko2_sel		168
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	cko2_podf		169
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	cko2			170
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	srtc_gate		171
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	pata_gate		172
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Examples (for mx53):
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			@ -110,6 +110,7 @@ enum imx5_clks {
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	owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
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	cko1_sel, cko1_podf, cko1,
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	cko2_sel, cko2_podf, cko2,
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	srtc_gate, pata_gate,
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	clk_max
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};
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			@ -266,6 +267,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
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	clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
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	clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
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	clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
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	clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
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	clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
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	for (i = 0; i < ARRAY_SIZE(clk); i++)
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		if (IS_ERR(clk[i]))
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