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tg3: make it possible to provide phy_id in ioctl

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In OpenWrt we currently use a switch driver which uses the ioctls to
configure the switch in the phy. We have to provide the phy_id to do
so, but without this patch this is not possible.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hauke Mehrtens 2013-02-07 05:37:38 +00:00 • committed by David S. Miller
commit 5c358045ae
1 changed files with 20 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

26
drivers/net/ethernet/broadcom/tg3.c
View file

@ -1091,7 +1091,8 @@ static void tg3_switch_clocks(struct tg3 *tp)
#define PHY_BUSY_LOOPS 5000 #define PHY_BUSY_LOOPS 5000
static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
u32 *val)
{ {
u32 frame_val; u32 frame_val;
unsigned int loops; unsigned int loops;
@ -1107,7 +1108,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
*val = 0x0; *val = 0x0;
frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK); MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK); MI_COM_REG_ADDR_MASK);
@ -1144,7 +1145,13 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
return ret; return ret;
} }
static int tg3_writephy(struct tg3 *tp, int reg, u32 val) static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
{
return __tg3_readphy(tp, tp->phy_addr, reg, val);
}
static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
u32 val)
{ {
u32 frame_val; u32 frame_val;
unsigned int loops; unsigned int loops;
@ -1162,7 +1169,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
tg3_ape_lock(tp, tp->phy_ape_lock); tg3_ape_lock(tp, tp->phy_ape_lock);
frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK); MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK); MI_COM_REG_ADDR_MASK);
@ -1197,6 +1204,11 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
return ret; return ret;
} }
static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
{
return __tg3_writephy(tp, tp->phy_addr, reg, val);
}
static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
{ {
int err; int err;
@ -12969,7 +12981,8 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
return -EAGAIN; return -EAGAIN;
spin_lock_bh(&tp->lock); spin_lock_bh(&tp->lock);
err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); err = __tg3_readphy(tp, data->phy_id & 0x1f,
data->reg_num & 0x1f, &mii_regval);
spin_unlock_bh(&tp->lock); spin_unlock_bh(&tp->lock);
data->val_out = mii_regval; data->val_out = mii_regval;
@ -12985,7 +12998,8 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
return -EAGAIN; return -EAGAIN;
spin_lock_bh(&tp->lock); spin_lock_bh(&tp->lock);
err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); err = __tg3_writephy(tp, data->phy_id & 0x1f,
data->reg_num & 0x1f, data->val_in);
spin_unlock_bh(&tp->lock); spin_unlock_bh(&tp->lock);
return err; return err;