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PCI: exynos: Split into Synopsys part and Exynos part

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Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.

Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
This commit is contained in:
Jingoo Han 2013-07-31 17:14:10 +09:00 • committed by Bjorn Helgaas
parent 5477a33b51
commit 4b1ced841b
6 changed files with 1000 additions and 866 deletions
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3
Documentation/devicetree/bindings/pci/designware-pcie.txt
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@ -18,6 +18,7 @@ Required properties:
- interrupt-map-mask and interrupt-map: standard PCI properties
to define the mapping of the PCIe interface to interrupt
numbers.
- num-lanes: number of lanes to use
- reset-gpio: gpio pin number of power good signal
Example:
@ -41,6 +42,7 @@ SoC specific DT Entry:
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0x0 0 &gic 53>;
num-lanes = <4>;
};
pcie@2a0000 {
@ -60,6 +62,7 @@ SoC specific DT Entry:
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0x0 0 &gic 56>;
num-lanes = <4>;
};
Board specific DT Entry: