brcmfmac: get chip core information from the device
Instead of instantiating core info structs based upon the chip identifier it is now done parsing information provided on the device. Reviewed-by: Franky (Zhenhui) Lin <frankyl@broadcom.com> Reviewed-by: Hante Meuleman <meuleman@broadcom.com> Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Daniel (Deognyoun) Kim <dekim@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Arend van Spriel
John W. Linville
parent
c5a9f3c193
commit
4aa2c47cd6
1 changed files with 203 additions and 104 deletions
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@ -32,6 +32,55 @@
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#define SOCI_SB 0
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#define SOCI_AI 1
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/* PL-368 DMP definitions */
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#define DMP_DESC_TYPE_MSK 0x0000000F
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#define DMP_DESC_EMPTY 0x00000000
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#define DMP_DESC_VALID 0x00000001
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#define DMP_DESC_COMPONENT 0x00000001
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#define DMP_DESC_MASTER_PORT 0x00000003
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#define DMP_DESC_ADDRESS 0x00000005
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#define DMP_DESC_ADDRSIZE_GT32 0x00000008
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#define DMP_DESC_EOT 0x0000000F
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#define DMP_COMP_DESIGNER 0xFFF00000
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#define DMP_COMP_DESIGNER_S 20
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#define DMP_COMP_PARTNUM 0x000FFF00
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#define DMP_COMP_PARTNUM_S 8
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#define DMP_COMP_CLASS 0x000000F0
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#define DMP_COMP_CLASS_S 4
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#define DMP_COMP_REVISION 0xFF000000
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#define DMP_COMP_REVISION_S 24
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#define DMP_COMP_NUM_SWRAP 0x00F80000
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#define DMP_COMP_NUM_SWRAP_S 19
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#define DMP_COMP_NUM_MWRAP 0x0007C000
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#define DMP_COMP_NUM_MWRAP_S 14
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#define DMP_COMP_NUM_SPORT 0x00003E00
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#define DMP_COMP_NUM_SPORT_S 9
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#define DMP_COMP_NUM_MPORT 0x000001F0
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#define DMP_COMP_NUM_MPORT_S 4
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#define DMP_MASTER_PORT_UID 0x0000FF00
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#define DMP_MASTER_PORT_UID_S 8
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#define DMP_MASTER_PORT_NUM 0x000000F0
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#define DMP_MASTER_PORT_NUM_S 4
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#define DMP_SLAVE_ADDR_BASE 0xFFFFF000
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#define DMP_SLAVE_ADDR_BASE_S 12
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#define DMP_SLAVE_PORT_NUM 0x00000F00
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#define DMP_SLAVE_PORT_NUM_S 8
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#define DMP_SLAVE_TYPE 0x000000C0
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#define DMP_SLAVE_TYPE_S 6
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#define DMP_SLAVE_TYPE_SLAVE 0
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#define DMP_SLAVE_TYPE_BRIDGE 1
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#define DMP_SLAVE_TYPE_SWRAP 2
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#define DMP_SLAVE_TYPE_MWRAP 3
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#define DMP_SLAVE_SIZE_TYPE 0x00000030
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#define DMP_SLAVE_SIZE_TYPE_S 4
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#define DMP_SLAVE_SIZE_4K 0
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#define DMP_SLAVE_SIZE_8K 1
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#define DMP_SLAVE_SIZE_16K 2
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#define DMP_SLAVE_SIZE_DESC 3
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/* EROM CompIdentB */
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#define CIB_REV_MASK 0xff000000
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#define CIB_REV_SHIFT 24
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@ -393,8 +442,9 @@ static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
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int idx = 1;
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list_for_each_entry(core, &ci->cores, list) {
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brcmf_dbg(INFO, " [%-2d] core 0x%x rev %-2d base 0x%08x\n",
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idx++, core->pub.id, core->pub.rev, core->pub.base);
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brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
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idx++, core->pub.id, core->pub.rev, core->pub.base,
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core->wrapbase);
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switch (core->pub.id) {
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case BCMA_CORE_ARM_CM3:
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@ -463,6 +513,151 @@ static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
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}
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}
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static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
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u8 *type)
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{
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u32 val;
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/* read next descriptor */
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val = ci->ops->read32(ci->ctx, *eromaddr);
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*eromaddr += 4;
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if (!type)
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return val;
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/* determine descriptor type */
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*type = (val & DMP_DESC_TYPE_MSK);
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if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
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*type = DMP_DESC_ADDRESS;
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return val;
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}
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static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
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u32 *regbase, u32 *wrapbase)
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{
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u8 desc;
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u32 val;
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u8 mpnum = 0;
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u8 stype, sztype, wraptype;
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*regbase = 0;
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*wrapbase = 0;
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val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
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if (desc == DMP_DESC_MASTER_PORT) {
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mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
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wraptype = DMP_SLAVE_TYPE_MWRAP;
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} else if (desc == DMP_DESC_ADDRESS) {
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/* revert erom address */
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*eromaddr -= 4;
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wraptype = DMP_SLAVE_TYPE_SWRAP;
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} else {
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*eromaddr -= 4;
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return -EILSEQ;
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}
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do {
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/* locate address descriptor */
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do {
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val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
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/* unexpected table end */
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if (desc == DMP_DESC_EOT) {
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*eromaddr -= 4;
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return -EFAULT;
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}
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} while (desc != DMP_DESC_ADDRESS);
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/* skip upper 32-bit address descriptor */
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if (val & DMP_DESC_ADDRSIZE_GT32)
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brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
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sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
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/* next size descriptor can be skipped */
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if (sztype == DMP_SLAVE_SIZE_DESC) {
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val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
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/* skip upper size descriptor if present */
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if (val & DMP_DESC_ADDRSIZE_GT32)
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brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
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}
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/* only look for 4K register regions */
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if (sztype != DMP_SLAVE_SIZE_4K)
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continue;
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stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
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/* only regular slave and wrapper */
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if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
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*regbase = val & DMP_SLAVE_ADDR_BASE;
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if (*wrapbase == 0 && stype == wraptype)
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*wrapbase = val & DMP_SLAVE_ADDR_BASE;
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} while (*regbase == 0 || *wrapbase == 0);
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return 0;
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}
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static
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int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
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{
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struct brcmf_core *core;
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u32 eromaddr;
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u8 desc_type = 0;
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u32 val;
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u16 id;
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u8 nmp, nsp, nmw, nsw, rev;
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u32 base, wrap;
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int err;
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eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
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while (desc_type != DMP_DESC_EOT) {
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val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
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if (!(val & DMP_DESC_VALID))
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continue;
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if (desc_type == DMP_DESC_EMPTY)
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continue;
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/* need a component descriptor */
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if (desc_type != DMP_DESC_COMPONENT)
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continue;
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id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
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/* next descriptor must be component as well */
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val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
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if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
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return -EFAULT;
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/* only look at cores with master port(s) */
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nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
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nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
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nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
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nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
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rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
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/* need core with ports */
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if (nmw + nsw == 0)
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continue;
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/* try to obtain register address info */
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err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
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if (err)
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continue;
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/* finally a core to be added */
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core = brcmf_chip_add_core(ci, id, base, wrap);
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if (IS_ERR(core))
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return PTR_ERR(core);
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core->rev = rev;
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}
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return 0;
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}
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static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
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{
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struct brcmf_core *core;
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@ -505,114 +700,21 @@ static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
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core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
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BCM4329_CORE_ARM_BASE, 0);
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brcmf_chip_sb_corerev(ci, core);
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core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
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brcmf_chip_sb_corerev(ci, core);
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} else if (socitype == SOCI_AI) {
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ci->iscoreup = brcmf_chip_ai_iscoreup;
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ci->coredisable = brcmf_chip_ai_coredisable;
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ci->resetcore = brcmf_chip_ai_resetcore;
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core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
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SI_ENUM_BASE,
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SI_ENUM_BASE + 0x100000);
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/* Address of cores for new chips should be added here */
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switch (ci->pub.chip) {
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case BCM43143_CHIP_ID:
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core->rev = 43;
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core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
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BCM43143_CORE_BUS_BASE,
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BCM43143_CORE_BUS_BASE +
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0x100000);
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core->rev = 24;
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core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
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BCM43143_CORE_SOCRAM_BASE,
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BCM43143_CORE_SOCRAM_BASE +
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0x100000);
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core->rev = 20;
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core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
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BCM43143_CORE_ARM_BASE,
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BCM43143_CORE_ARM_BASE +
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0x100000);
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core->rev = 7;
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break;
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case BCM43241_CHIP_ID:
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core->rev = 42;
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core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
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0x18002000, 0x18102000);
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core->rev = 14;
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core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
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0x18004000, 0x18104000);
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core->rev = 20;
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core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
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0x18003000, 0x18103000);
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core->rev = 7;
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break;
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case BCM4330_CHIP_ID:
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core->rev = 39;
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core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
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0x18002000, 0x18102000);
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core->rev = 7;
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core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
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0x18004000, 0x18104000);
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core->rev = 13;
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core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
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0x18003000, 0x18103000);
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core->rev = 3;
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break;
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case BCM4334_CHIP_ID:
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core->rev = 41;
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core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
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0x18002000, 0x18102000);
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core->rev = 13;
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core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
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0x18004000, 0x18104000);
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core->rev = 19;
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core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
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0x18003000, 0x18103000);
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core->rev = 7;
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break;
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case BCM4335_CHIP_ID:
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core->rev = 43;
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core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
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0x18005000, 0x18105000);
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core->rev = 15;
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core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CR4,
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0x18002000, 0x18102000);
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core->rev = 1;
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break;
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case BCM43362_CHIP_ID:
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core->rev = 39;
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core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
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0x18002000, 0x18102000);
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core->rev = 10;
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core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
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0x18004000, 0x18104000);
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core->rev = 8;
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core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
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0x18003000, 0x18103000);
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core->rev = 3;
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break;
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case BCM4339_CHIP_ID:
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core->rev = 46;
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core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
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0x18005000, 0x18105000);
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core->rev = 21;
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core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CR4,
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0x18002000, 0x18102000);
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core->rev = 4;
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break;
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default:
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brcmf_err("AXI chip is not supported\n");
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return -ENODEV;
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}
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brcmf_chip_dmp_erom_scan(ci);
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} else {
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brcmf_err("chip backplane type %u is not supported\n",
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socitype);
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return -ENODEV;
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}
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/* add 802.11 core for all chips on same backplane address */
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core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0x18101000);
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brcmf_chip_get_raminfo(ci);
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return brcmf_chip_cores_check(ci);
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@ -652,7 +754,6 @@ static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
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{
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struct brcmf_chip *pub;
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struct brcmf_core_priv *cc;
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struct brcmf_core_priv *bus;
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u32 base;
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u32 val;
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int ret = 0;
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@ -673,10 +774,8 @@ static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
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pub->pmucaps = val;
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}
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bus = list_next_entry(cc, list);
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brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
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cc->pub.rev, pub->pmurev, bus->pub.rev, bus->pub.id);
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brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
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cc->pub.rev, pub->pmurev, pub->pmucaps);
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/* execute bus core specific setup */
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if (chip->ops->setup)
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