PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
"msi_attrib.pos" is only used for MSI (not MSI-X), and we already cache the MSI capability offset in "dev->msi_cap". Remove "pos" from the struct msi_attrib and use "dev->msi_cap" directly. [bhelgaas: changelog, fix whitespace] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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					 4 changed files with 4 additions and 10 deletions
				
			
		|  | @ -73,8 +73,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) | ||||||
| 	 * wants.  Most devices only want 1, which will give | 	 * wants.  Most devices only want 1, which will give | ||||||
| 	 * configured_private_bits and request_private_bits equal 0. | 	 * configured_private_bits and request_private_bits equal 0. | ||||||
| 	 */ | 	 */ | ||||||
| 	pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, | 	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | ||||||
| 			     &control); |  | ||||||
| 
 | 
 | ||||||
| 	/*
 | 	/*
 | ||||||
| 	 * If the number of private bits has been configured then use | 	 * If the number of private bits has been configured then use | ||||||
|  | @ -176,8 +175,7 @@ msi_irq_allocated: | ||||||
| 	/* Update the number of IRQs the device has available to it */ | 	/* Update the number of IRQs the device has available to it */ | ||||||
| 	control &= ~PCI_MSI_FLAGS_QSIZE; | 	control &= ~PCI_MSI_FLAGS_QSIZE; | ||||||
| 	control |= request_private_bits << 4; | 	control |= request_private_bits << 4; | ||||||
| 	pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, | 	pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | ||||||
| 			      control); |  | ||||||
| 
 | 
 | ||||||
| 	irq_set_msi_desc(irq, desc); | 	irq_set_msi_desc(irq, desc); | ||||||
| 	write_msi_msg(irq, &msg); | 	write_msi_msg(irq, &msg); | ||||||
|  |  | ||||||
|  | @ -355,8 +355,7 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, | ||||||
| 		return -EINVAL; | 		return -EINVAL; | ||||||
| 	} | 	} | ||||||
| 
 | 
 | ||||||
| 	pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS, | 	pci_read_config_word(pdev, pdev->msi_cap + PCI_MSI_FLAGS, &msg_ctr); | ||||||
| 				&msg_ctr); |  | ||||||
| 	msgvec = (msg_ctr & PCI_MSI_FLAGS_QSIZE) >> 4; | 	msgvec = (msg_ctr & PCI_MSI_FLAGS_QSIZE) >> 4; | ||||||
| 	if (msgvec == 0) | 	if (msgvec == 0) | ||||||
| 		msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1; | 		msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1; | ||||||
|  |  | ||||||
|  | @ -574,7 +574,6 @@ static struct msi_desc *msi_setup_entry(struct pci_dev *dev) | ||||||
| 	entry->msi_attrib.entry_nr	= 0; | 	entry->msi_attrib.entry_nr	= 0; | ||||||
| 	entry->msi_attrib.maskbit	= !!(control & PCI_MSI_FLAGS_MASKBIT); | 	entry->msi_attrib.maskbit	= !!(control & PCI_MSI_FLAGS_MASKBIT); | ||||||
| 	entry->msi_attrib.default_irq	= dev->irq;	/* Save IOAPIC IRQ */ | 	entry->msi_attrib.default_irq	= dev->irq;	/* Save IOAPIC IRQ */ | ||||||
| 	entry->msi_attrib.pos		= dev->msi_cap; |  | ||||||
| 	entry->msi_attrib.multi_cap	= (control & PCI_MSI_FLAGS_QMASK) >> 1; | 	entry->msi_attrib.multi_cap	= (control & PCI_MSI_FLAGS_QMASK) >> 1; | ||||||
| 
 | 
 | ||||||
| 	if (control & PCI_MSI_FLAGS_64BIT) | 	if (control & PCI_MSI_FLAGS_64BIT) | ||||||
|  | @ -678,7 +677,6 @@ static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, | ||||||
| 		entry->msi_attrib.is_64		= 1; | 		entry->msi_attrib.is_64		= 1; | ||||||
| 		entry->msi_attrib.entry_nr	= entries[i].entry; | 		entry->msi_attrib.entry_nr	= entries[i].entry; | ||||||
| 		entry->msi_attrib.default_irq	= dev->irq; | 		entry->msi_attrib.default_irq	= dev->irq; | ||||||
| 		entry->msi_attrib.pos		= dev->msix_cap; |  | ||||||
| 		entry->mask_base		= base; | 		entry->mask_base		= base; | ||||||
| 
 | 
 | ||||||
| 		list_add_tail(&entry->list, &dev->msi_list); | 		list_add_tail(&entry->list, &dev->msi_list); | ||||||
|  |  | ||||||
|  | @ -29,7 +29,6 @@ struct msi_desc { | ||||||
| 		__u8	multi_cap : 3;	/* log2 num of messages supported */ | 		__u8	multi_cap : 3;	/* log2 num of messages supported */ | ||||||
| 		__u8	maskbit	: 1;	/* mask-pending bit supported ? */ | 		__u8	maskbit	: 1;	/* mask-pending bit supported ? */ | ||||||
| 		__u8	is_64	: 1;	/* Address size: 0=32bit 1=64bit */ | 		__u8	is_64	: 1;	/* Address size: 0=32bit 1=64bit */ | ||||||
| 		__u8	pos;		/* Location of the msi capability */ |  | ||||||
| 		__u16	entry_nr;	/* specific enabled entry */ | 		__u16	entry_nr;	/* specific enabled entry */ | ||||||
| 		unsigned default_irq;	/* default pre-assigned irq */ | 		unsigned default_irq;	/* default pre-assigned irq */ | ||||||
| 	} msi_attrib; | 	} msi_attrib; | ||||||
|  |  | ||||||
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	 Yijing Wang
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