Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Conflicts: drivers/firmware/iscsi_ibft.c
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David S. Miller
commit
47871889c6
2090 changed files with 104065 additions and 45054 deletions
70
Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt
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70
Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt
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@ -0,0 +1,70 @@
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MPC5121 PSC Device Tree Bindings
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PSC in UART mode
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----------------
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For PSC in UART mode the needed PSC serial devices
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are specified by fsl,mpc5121-psc-uart nodes in the
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fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
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Controller node fsl,mpc5121-psc-fifo is requered there:
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fsl,mpc5121-psc-uart nodes
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--------------------------
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Required properties :
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- compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
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- cell-index : Index of the PSC in hardware
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- reg : Offset and length of the register set for the PSC device
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- interrupts : <a b> where a is the interrupt number of the
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PSC FIFO Controller and b is a field that represents an
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encoding of the sense and level information for the interrupt.
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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Recommended properties :
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- fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
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- fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
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fsl,mpc5121-psc-fifo node
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-------------------------
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Required properties :
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- compatible : Should be "fsl,mpc5121-psc-fifo"
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- reg : Offset and length of the register set for the PSC
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FIFO Controller
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- interrupts : <a b> where a is the interrupt number of the
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PSC FIFO Controller and b is a field that represents an
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encoding of the sense and level information for the interrupt.
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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Example for a board using PSC0 and PSC1 devices in serial mode:
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serial@11000 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <0>;
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reg = <0x11000 0x100>;
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interrupts = <40 0x8>;
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interrupt-parent = < &ipic >;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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serial@11100 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <1>;
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reg = <0x11100 0x100>;
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interrupts = <40 0x8>;
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interrupt-parent = < &ipic >;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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pscfifo@11f00 {
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compatible = "fsl,mpc5121-psc-fifo";
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reg = <0x11f00 0x100>;
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interrupts = <40 0x8>;
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interrupt-parent = < &ipic >;
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};
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@ -13,6 +13,11 @@ Required properties:
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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Optional properties:
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- gpios : specifies the gpio pins to be used for chipselects.
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The gpios will be referred to as reg = <index> in the SPI child nodes.
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If unspecified, a single SPI device without a chip select can be used.
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Example:
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spi@4c0 {
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cell-index = <0>;
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@ -21,4 +26,6 @@ Example:
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interrupts = <82 0>;
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interrupt-parent = <700>;
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mode = "cpu";
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gpios = <&gpio 18 1 // device reg=<0>
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&gpio 19 1>; // device reg=<1>
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};
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134
Documentation/powerpc/ptrace.txt
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134
Documentation/powerpc/ptrace.txt
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GDB intends to support the following hardware debug features of BookE
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processors:
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4 hardware breakpoints (IAC)
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2 hardware watchpoints (read, write and read-write) (DAC)
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2 value conditions for the hardware watchpoints (DVC)
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For that, we need to extend ptrace so that GDB can query and set these
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resources. Since we're extending, we're trying to create an interface
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that's extendable and that covers both BookE and server processors, so
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that GDB doesn't need to special-case each of them. We added the
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following 3 new ptrace requests.
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1. PTRACE_PPC_GETHWDEBUGINFO
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Query for GDB to discover the hardware debug features. The main info to
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be returned here is the minimum alignment for the hardware watchpoints.
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BookE processors don't have restrictions here, but server processors have
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an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid
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adding special cases to GDB based on what it sees in AUXV.
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Since we're at it, we added other useful info that the kernel can return to
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GDB: this query will return the number of hardware breakpoints, hardware
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watchpoints and whether it supports a range of addresses and a condition.
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The query will fill the following structure provided by the requesting process:
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struct ppc_debug_info {
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unit32_t version;
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unit32_t num_instruction_bps;
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unit32_t num_data_bps;
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unit32_t num_condition_regs;
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unit32_t data_bp_alignment;
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unit32_t sizeof_condition; /* size of the DVC register */
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uint64_t features; /* bitmask of the individual flags */
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};
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features will have bits indicating whether there is support for:
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#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
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#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
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#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
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#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
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2. PTRACE_SETHWDEBUG
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Sets a hardware breakpoint or watchpoint, according to the provided structure:
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struct ppc_hw_breakpoint {
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uint32_t version;
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#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
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#define PPC_BREAKPOINT_TRIGGER_READ 0x2
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#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
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uint32_t trigger_type; /* only some combinations allowed */
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#define PPC_BREAKPOINT_MODE_EXACT 0x0
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#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
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#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
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#define PPC_BREAKPOINT_MODE_MASK 0x3
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uint32_t addr_mode; /* address match mode */
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#define PPC_BREAKPOINT_CONDITION_MODE 0x3
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#define PPC_BREAKPOINT_CONDITION_NONE 0x0
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#define PPC_BREAKPOINT_CONDITION_AND 0x1
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#define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same thing as above */
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#define PPC_BREAKPOINT_CONDITION_OR 0x2
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#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
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#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */
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#define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16))
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uint32_t condition_mode; /* break/watchpoint condition flags */
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uint64_t addr;
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uint64_t addr2;
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uint64_t condition_value;
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};
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A request specifies one event, not necessarily just one register to be set.
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For instance, if the request is for a watchpoint with a condition, both the
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DAC and DVC registers will be set in the same request.
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With this GDB can ask for all kinds of hardware breakpoints and watchpoints
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that the BookE supports. COMEFROM breakpoints available in server processors
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are not contemplated, but that is out of the scope of this work.
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ptrace will return an integer (handle) uniquely identifying the breakpoint or
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watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG
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request to ask for its removal. Return -ENOSPC if the requested breakpoint
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can't be allocated on the registers.
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Some examples of using the structure to:
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- set a breakpoint in the first breakpoint register
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p.version = PPC_DEBUG_CURRENT_VERSION;
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p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
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p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
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p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
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p.addr = (uint64_t) address;
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p.addr2 = 0;
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p.condition_value = 0;
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- set a watchpoint which triggers on reads in the second watchpoint register
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p.version = PPC_DEBUG_CURRENT_VERSION;
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p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
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p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
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p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
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p.addr = (uint64_t) address;
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p.addr2 = 0;
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p.condition_value = 0;
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- set a watchpoint which triggers only with a specific value
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p.version = PPC_DEBUG_CURRENT_VERSION;
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p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ;
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p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
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p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL;
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p.addr = (uint64_t) address;
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p.addr2 = 0;
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p.condition_value = (uint64_t) condition;
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- set a ranged hardware breakpoint
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p.version = PPC_DEBUG_CURRENT_VERSION;
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p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
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p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
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p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
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p.addr = (uint64_t) begin_range;
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p.addr2 = (uint64_t) end_range;
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p.condition_value = 0;
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3. PTRACE_DELHWDEBUG
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Takes an integer which identifies an existing breakpoint or watchpoint
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(i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the
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corresponding breakpoint or watchpoint..
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