powerpc: Free up some CPU feature bits by moving out MMU-related features
Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Matt Evans
Benjamin Herrenschmidt
parent
eca590f402
commit
44ae3ab335
20 changed files with 132 additions and 96 deletions
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@ -178,23 +178,17 @@ extern const char *powerpc_base_platform;
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#define LONG_ASM_CONST(x) 0
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#endif
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#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
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#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
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#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
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#define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x0000000800000000)
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#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
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#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
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#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
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#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
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#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
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#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
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#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
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#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
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#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
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#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
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#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
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#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
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#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
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#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
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#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
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#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
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@ -206,9 +200,10 @@ extern const char *powerpc_base_platform;
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#ifndef __ASSEMBLY__
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#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
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CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
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CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
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#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
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#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
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MMU_FTR_16M_PAGE)
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/* We only set the altivec features if the kernel was compiled with altivec
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* support
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@ -408,38 +403,34 @@ extern const char *powerpc_base_platform;
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#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
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CPU_FTR_POPCNTB)
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
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#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_COHERENT_ICACHE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
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#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_COHERENT_ICACHE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
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#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
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CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
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CPU_FTR_UNALIGNED_LD_STD)
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#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
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CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_PURR | CPU_FTR_REAL_LE)
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#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
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#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
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CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
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CPU_FTR_16M_PAGE)
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CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
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#ifdef __powerpc64__
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#ifdef CONFIG_PPC_BOOK3E
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@ -449,7 +440,7 @@ extern const char *powerpc_base_platform;
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(CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
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CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
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CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
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CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
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CPU_FTR_VSX)
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#endif
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#else
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enum {
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@ -70,6 +70,54 @@
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*/
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#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
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/* MMU is SLB-based
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*/
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#define MMU_FTR_SLB ASM_CONST(0x02000000)
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/* Support 16M large pages
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*/
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#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
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/* Supports TLBIEL variant
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*/
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#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
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/* Supports tlbies w/o locking
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*/
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#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
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/* Large pages can be marked CI
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*/
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#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
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/* 1T segments available
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*/
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#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
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/* Doesn't support the B bit (1T segment) in SLBIE
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*/
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#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
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/* MMU feature bit sets for various CPUs */
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#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
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MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
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#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
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#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
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#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
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#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
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#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | \
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MMU_FTR_TLBIE_206
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#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
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MMU_FTR_CI_LARGE_PAGE
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#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
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MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
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#define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
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MMU_FTR_USE_TLBIVAX_BCAST | \
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MMU_FTR_LOCK_BCAST_INVAL | \
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MMU_FTR_USE_TLBRSRV | \
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MMU_FTR_USE_PAIRED_MAS | \
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MMU_FTR_TLBIEL | \
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MMU_FTR_16M_PAGE
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#ifndef __ASSEMBLY__
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#include <asm/cputable.h>
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@ -67,7 +67,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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* sub architectures.
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*/
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#ifdef CONFIG_PPC_STD_MMU_64
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if (cpu_has_feature(CPU_FTR_SLB))
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if (mmu_has_feature(MMU_FTR_SLB))
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switch_slb(tsk, next);
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else
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switch_stab(tsk, next);
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