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drm/i915/skl: Adjust get_plane_config() to support Yb/Yf tiling

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v2: Rebased for addfb2 interface and consolidated a bit. (Tvrtko Ursulin)
v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
v4: Use intel_fb_stride_alignment instead of open coding. (Damien Lespiau)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau 2015-02-27 11:15:21 +00:00 • committed by Daniel Vetter
parent 1327b9a1d5
commit 40f4628391
1 changed files with 23 additions and 17 deletions
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40
drivers/gpu/drm/i915/intel_display.c
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@ -7740,7 +7740,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
{ {
struct drm_device *dev = crtc->base.dev; struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
u32 val, base, offset, stride_mult; u32 val, base, offset, stride_mult, tiling;
int pipe = crtc->pipe; int pipe = crtc->pipe;
int fourcc, pixel_format; int fourcc, pixel_format;
int aligned_height; int aligned_height;
@ -7759,11 +7759,6 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
if (!(val & PLANE_CTL_ENABLE)) if (!(val & PLANE_CTL_ENABLE))
goto error; goto error;
if (val & PLANE_CTL_TILED_MASK) {
plane_config->tiling = I915_TILING_X;
fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
}
pixel_format = val & PLANE_CTL_FORMAT_MASK; pixel_format = val & PLANE_CTL_FORMAT_MASK;
fourcc = skl_format_to_fourcc(pixel_format, fourcc = skl_format_to_fourcc(pixel_format,
val & PLANE_CTL_ORDER_RGBX, val & PLANE_CTL_ORDER_RGBX,
@ -7771,6 +7766,26 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->pixel_format = fourcc; fb->pixel_format = fourcc;
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
tiling = val & PLANE_CTL_TILED_MASK;
switch (tiling) {
case PLANE_CTL_TILED_LINEAR:
fb->modifier[0] = DRM_FORMAT_MOD_NONE;
break;
case PLANE_CTL_TILED_X:
plane_config->tiling = I915_TILING_X;
fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
break;
case PLANE_CTL_TILED_Y:
fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
break;
case PLANE_CTL_TILED_YF:
fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
break;
default:
MISSING_CASE(tiling);
goto error;
}
base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
plane_config->base = base; plane_config->base = base;
@ -7781,17 +7796,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->width = ((val >> 0) & 0x1fff) + 1; fb->width = ((val >> 0) & 0x1fff) + 1;
val = I915_READ(PLANE_STRIDE(pipe, 0)); val = I915_READ(PLANE_STRIDE(pipe, 0));
switch (plane_config->tiling) { stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
case I915_TILING_NONE: fb->pixel_format);
stride_mult = 64;
break;
case I915_TILING_X:
stride_mult = 512;
break;
default:
MISSING_CASE(plane_config->tiling);
goto error;
}
fb->pitches[0] = (val & 0x3ff) * stride_mult; fb->pitches[0] = (val & 0x3ff) * stride_mult;
aligned_height = intel_fb_align_height(dev, fb->height, aligned_height = intel_fb_align_height(dev, fb->height,